| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| r6.s | 231 jic $3,-32768
232 jic $3,32767
|
| r6-n32.d | 455 0+0518 <[^>]*> d8038000 jic v1,-32768
456 0+051c <[^>]*> d8037fff jic v1,32767
|
| r6.d | 454 0+0518 <[^>]*> d8038000 jic v1,-32768
455 0+051c <[^>]*> d8037fff jic v1,32767
|
| r6-n64.d | 691 0+0518 <[^>]*> d8038000 jic v1,-32768
692 0+051c <[^>]*> d8037fff jic v1,32767
|
| /art/runtime/interpreter/mterp/mips64/ |
| header.S | 159 jic AT, 0
|
| /external/v8/test/cctest/ |
| test-disasm-mips.cc | [all...] |
| test-disasm-mips64.cc | 784 COMPARE(jic(t0, 16), "d80c0010 jic t0, 16");
785 COMPARE(jic(t0, 4), "d80c0004 jic t0, 4");
786 COMPARE(jic(t0, -32), "d80cffe0 jic t0, -32");
[all...] |
| test-assembler-mips.cc | [all...] |
| test-assembler-mips64.cc | [all...] |
| /external/llvm/test/MC/Mips/micromips32r6/ |
| valid.s | 55 jic $5, 256 # CHECK: jic $5, 256 # encoding: [0xa0,0x05,0x01,0x00]
|
| /external/v8/src/mips64/ |
| disasm-mips64.cc | [all...] |
| assembler-mips64.h | 722 void jic(Register rt, int16_t offset);
[all...] |
| assembler-mips64.cc | 1567 void Assembler::jic(Register rt, int16_t offset) { function in class:v8::internal::Assembler
[all...] |
| macro-assembler-mips64.cc | [all...] |
| /external/v8/src/mips/ |
| assembler-mips.h | 713 void jic(Register rt, int16_t offset);
[all...] |
| assembler-mips.cc | 745 // Use just lui and jic instructions. Insert lower part of the target address in
746 // jic offset part. Since jic sign-extends offset and then add it with register,
749 // in jic register with lui instruction.
1569 void Assembler::jic(Register rt, int16_t offset) { function in class:v8::Assembler
[all...] |
| macro-assembler-mips.cc | [all...] |
| /art/runtime/interpreter/mterp/out/ |
| mterp_mips64.S | 166 jic AT, 0
[all...] |
