| /external/clang/test/CodeGen/ |
| atomic.c | 5 int old; local
13 old = __sync_fetch_and_add(&val, 1);
16 old = __sync_fetch_and_sub(&valc, 2);
19 old = __sync_fetch_and_min(&val, 3);
22 old = __sync_fetch_and_max(&val, 4);
25 old = __sync_fetch_and_umin(&uval, 5u);
28 old = __sync_fetch_and_umax(&uval, 6u);
31 old = __sync_lock_test_and_set(&val, 7);
34 old = __sync_swap(&val, 8);
37 old = __sync_val_compare_and_swap(&val, 4, 1976)
[all...] |
| /external/icu/icu4c/source/tools/tzcode/ |
| ialloc.c | 11 icatalloc(char *const old, const char *const new)
17 if (old == NULL)
20 return old;
21 else oldsize = strlen(old);
22 if ((result = realloc(old, oldsize + newsize + 1)) != NULL)
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/util/ |
| atomic.hpp | 74 int old = *address_as_i, assumed;
76 assumed = old;
77 old = ::atomicCAS(address_as_i, assumed,
79 } while (assumed != old);
80 return __int_as_float(old);
88 unsigned long long int old = *address_as_ull, assumed; local
90 assumed = old;
91 old = ::atomicCAS(address_as_ull, assumed,
93 } while (assumed != old);
94 return __longlong_as_double(old);
118 int old = *address_as_i, assumed; local
136 unsigned long long int old = *address_as_ull, assumed; local
166 int old = *address_as_i, assumed; local
184 unsigned long long int old = *address_as_ull, assumed; local
[all...] |
| /device/google/contexthub/firmware/src/cpu/x86/ |
| atomic.c | 21 uint32_t old; local
24 old = *val;
25 } while (!atomicCmpXchg32bits(val, old, old + addend));
27 return old;
32 uint8_t old; local
35 old = *val;
36 } while (!atomicCmpXchgByte(val, old, old + addend));
38 return old;
[all...] |
| atomicBitset.c | 49 uint32_t old, new; local
56 old = *wordPtr;
57 new = old &~ mask;
58 } while (!atomicCmpXchg32bits(wordPtr, old, new));
67 uint32_t old, new; local
70 old = *wordPtr;
71 if (!(old + 1)) /* no work for words with no clear bits */
74 pos = __builtin_ctz(~old); /* This will allocate in diff order than ARM. Since we never made any promises on order of bits returned, this is ok */
75 new = old | (1 << pos);
77 if (atomicCmpXchg32bits(wordPtr, old, new)
[all...] |
| /external/e2fsprogs/lib/ext2fs/ |
| brel.h | 37 errcode_t (*put)(ext2_brel brel, blk64_t old,
43 errcode_t (*get)(ext2_brel brel, blk64_t old,
55 errcode_t (*next)(ext2_brel brel, blk64_t *old,
62 errcode_t (*move)(ext2_brel brel, blk64_t old, blk_t new);
67 errcode_t (*delete)(ext2_brel brel, blk64_t old);
79 #define ext2fs_brel_put(brel, old, ent) ((brel)->put((brel), old, ent))
80 #define ext2fs_brel_get(brel, old, ent) ((brel)->get((brel), old, ent))
82 #define ext2fs_brel_next(brel, old, ent) ((brel)->next((brel), old, ent)
[all...] |
| irel.h | 35 errcode_t (*put)(ext2_irel irel, ext2_ino_t old,
40 errcode_t (*get)(ext2_irel irel, ext2_ino_t old,
46 errcode_t (*get_by_orig)(ext2_irel irel, ext2_ino_t orig, ext2_ino_t *old,
58 errcode_t (*next)(ext2_irel irel, ext2_ino_t *old,
86 errcode_t (*move)(ext2_irel irel, ext2_ino_t old, ext2_ino_t new);
92 errcode_t (*delete)(ext2_irel irel, ext2_ino_t old);
103 #define ext2fs_irel_put(irel, old, ent) ((irel)->put((irel), old, ent))
104 #define ext2fs_irel_get(irel, old, ent) ((irel)->get((irel), old, ent)
[all...] |
| /external/clang/test/SemaCXX/ |
| constexpr-turing.cpp | 19 constexpr Tape(const Tape &old, bool write) :
20 l(old.l), val(write), r(old.r) {}
21 constexpr Tape(const Tape &old, Dir dir) :
22 l(dir == L ? old.l ? old.l->l : 0 : &old),
23 val(dir == L ? old.l ? old.l->val : false
24 : old.r ? old.r->val : false)
[all...] |
| /bionic/libc/arch-arm/bionic/ |
| atomics_arm.c | 61 __atomic_cmpxchg(int old, int _new, volatile int *ptr)
64 return __sync_val_compare_and_swap(ptr, old, _new) != old;
|
| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_update_shadow_word_inl.h | 20 old = LoadShadow(sp);
21 if (old.IsZero()) {
30 if (Shadow::Addr0AndSizeAreEqual(cur, old)) {
33 if (Shadow::TidsAreEqual(old, cur)) {
35 if (old.IsRWWeakerOrEqual(kAccessIsWrite, kIsAtomic))
40 if (HappensBefore(old, thr)) {
41 if (old.IsRWWeakerOrEqual(kAccessIsWrite, kIsAtomic))
45 if (old.IsBothReadsOrAtomic(kAccessIsWrite, kIsAtomic))
50 if (Shadow::TwoRangesIntersect(old, cur, kAccessSize)) {
52 if (Shadow::TidsAreEqual(old, cur))
[all...] |
| /external/libcxx/test/std/depr/exception.unexpected/set.unexpected/ |
| set_unexpected.pass.cpp | 26 std::unexpected_handler old = std::set_unexpected(f1); local
28 assert(old);
33 (*old)();
|
| /ndk/sources/cxx-stl/llvm-libc++/libcxx/test/depr/exception.unexpected/set.unexpected/ |
| set_unexpected.pass.cpp | 26 std::unexpected_handler old = std::set_unexpected(f1); local
28 assert(old);
36 (*old)();
|
| /external/strace/tests/ |
| timer_xettime.c | 57 } old = { local
67 if (syscall(__NR_timer_settime, tid, 0, &new.its, &old.its))
78 (intmax_t) old.its.it_interval.tv_sec,
79 (intmax_t) old.its.it_interval.tv_nsec,
80 (intmax_t) old.its.it_value.tv_sec,
81 (intmax_t) old.its.it_value.tv_nsec);
83 if (syscall(__NR_timer_gettime, tid, &old.its))
89 (intmax_t) old.its.it_interval.tv_sec,
90 (intmax_t) old.its.it_interval.tv_nsec,
91 (intmax_t) old.its.it_value.tv_sec
[all...] |
| timerfd_xettime.c | 55 } old = { local
65 if (syscall(__NR_timerfd_settime, 0, 0, &new.its, &old.its))
75 (intmax_t) old.its.it_interval.tv_sec,
76 (intmax_t) old.its.it_interval.tv_nsec,
77 (intmax_t) old.its.it_value.tv_sec,
78 (intmax_t) old.its.it_value.tv_nsec);
80 if (syscall(__NR_timerfd_gettime, 0, &old.its))
85 (intmax_t) old.its.it_interval.tv_sec,
86 (intmax_t) old.its.it_interval.tv_nsec,
87 (intmax_t) old.its.it_value.tv_sec
[all...] |
| xetitimer.c | 38 } old = { local
48 if (setitimer(ITIMER_REAL, &new.itv, &old.itv))
58 (intmax_t) old.itv.it_interval.tv_sec,
59 (intmax_t) old.itv.it_interval.tv_usec,
60 (intmax_t) old.itv.it_value.tv_sec,
61 (intmax_t) old.itv.it_value.tv_usec);
63 if (getitimer(ITIMER_REAL, &old.itv))
68 (intmax_t) old.itv.it_interval.tv_sec,
69 (intmax_t) old.itv.it_interval.tv_usec,
70 (intmax_t) old.itv.it_value.tv_sec
[all...] |
| /development/ndk/platforms/android-9/arch-mips/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-12/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-13/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-14/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-15/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-16/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-17/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
[all...] |
| /prebuilts/ndk/current/platforms/android-18/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
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| /prebuilts/ndk/current/platforms/android-19/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
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| /prebuilts/ndk/current/platforms/android-9/arch-mips/usr/include/asm/ |
| cmpxchg.h | 24 #define __cmpxchg_asm(ld, st, m, old, new) ({ __typeof(*(m)) __ret; if (cpu_has_llsc && R10000_LLSC_WAR) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqzl $1, 1b \n" "2: \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else if (cpu_has_llsc) { __asm__ __volatile__( " .set push \n" " .set noat \n" " .set mips3 \n" "1: " ld " %0, %2 # __cmpxchg_asm \n" " bne %0, %z3, 2f \n" " .set mips0 \n" " move $1, %z4 \n" " .set mips3 \n" " " st " $1, %1 \n" " beqz $1, 3f \n" "2: \n" " .subsection 2 \n" "3: b 1b \n" " .previous \n" " .set pop \n" : "=&r" (__ret), "=R" (*m) : "R" (*m), "Jr" (old), "Jr" (new) : "memory"); } else { unsigned long __flags; raw_local_irq_save(__flags); __ret = *m; if (__ret == old) *m = new; raw_local_irq_restore(__flags); } __ret; })
25 #define __cmpxchg(ptr, old, new, barrier) ({ __typeof__(ptr) __ptr = (ptr); __typeof__(*(ptr)) __old = (old); __typeof__(*(ptr)) __new = (new); __typeof__(*(ptr)) __res = 0; barrier; switch (sizeof(*(__ptr))) { case 4: __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); break; case 8: if (sizeof(long) == 8) { __res = __cmpxchg_asm("lld", "scd", __ptr, __old, __new); break; } default: __cmpxchg_called_with_bad_pointer(); break; } barrier; __res; })
26 #define cmpxchg(ptr, old, new) __cmpxchg(ptr, old, new, smp_llsc_mb())
27 #define cmpxchg_local(ptr, old, new) __cmpxchg(ptr, old, new,
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