/art/runtime/interpreter/mterp/x86/ |
op_goto.S | 8 movsbl rINSTbl, rINST # rINST <- ssssssAA 9 testl rINST, rINST
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op_goto_16.S | 8 movswl 2(rPC), rINST # rINST <- ssssAAAA 9 testl rINST, rINST
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op_goto_32.S | 13 movl 2(rPC), rINST # rINST <- AAAAAAAA 14 testl rINST, rINST
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op_const_4.S | 3 movl $$0xf, rINST 4 andl %eax, rINST # rINST <- A 6 SET_VREG %eax, rINST
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op_array_length.S | 4 mov rINST, %eax # eax <- BA 5 sarl $$4, rINST # rINST <- B 6 GET_VREG %ecx, rINST # ecx <- vB (object ref) 10 movl MIRROR_ARRAY_LENGTH_OFFSET(%ecx), rINST 11 SET_VREG rINST, %eax
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op_move.S | 6 shrl $$4, rINST # rINST <- B 7 GET_VREG rINST, rINST 9 SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] 11 SET_VREG rINST, %eax # fp[A] <- fp[B]
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zcmp.S | 9 cmpl $$0, VREG_ADDRESS(rINST) # compare (vA, 0) 11 movswl 2(rPC), rINST # fetch signed displacement 12 testl rINST, rINST
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op_move_from16.S | 6 GET_VREG rINST, rINST # rINST <- fp[BBBB] 8 SET_VREG_OBJECT rINST, %eax # fp[A] <- fp[B] 10 SET_VREG rINST, %eax # fp[A] <- fp[B]
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op_mul_int_2addr.S | 3 sarl $$4, rINST # rINST <- B 4 GET_VREG %eax, rINST # eax <- vB 6 movl rIBASE, rINST 8 movl rINST, rIBASE
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binop2addr.S | 14 sarl $$4, rINST # rINST <- B 15 GET_VREG %eax, rINST # eax <- vB
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op_const_wide.S | 4 movl 6(rPC), rINST # rINST <- msw 6 SET_VREG_HIGH rINST, %ecx
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op_move_wide.S | 4 sarl $$4, rINST # rINST <- B 6 GET_WIDE_FP_VREG %xmm0, rINST # xmm0 <- v[B]
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unop.S | 8 sarl $$4,rINST # rINST <- B 9 GET_VREG %eax, rINST # eax <- vB
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/art/runtime/interpreter/mterp/arm/ |
op_goto.S | 8 sbfx rINST, rINST, #8, #8 @ rINST<- ssssssAA (sign-extended)
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op_goto_16.S | 8 FETCH_S rINST, 1 @ rINST<- ssssAAAA (sign-extended)
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op_move_result_wide.S | 2 mov rINST, rINST, lsr #8 @ rINST<- AA 4 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] 6 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 7 FETCH_ADVANCE_INST 1 @ advance rPC, load rINST 9 GET_INST_OPCODE ip @ extract opcode from rINST
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op_move_wide_from16.S | 4 mov rINST, rINST, lsr #8 @ rINST<- AA 6 VREG_INDEX_TO_ADDR r2, rINST @ r2<- &fp[AA] 8 CLEAR_SHADOW_PAIR rINST, ip, lr @ Zero out the shadow regs 9 FETCH_ADVANCE_INST 2 @ advance rPC, load rINST 10 GET_INST_OPCODE ip @ extract opcode from rINST
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/art/runtime/interpreter/mterp/mips64/ |
fcvtHeader.S | 12 ext a1, rINST, 8, 4 # a1 <- A 13 srl a2, rINST, 12 # a2 <- B 15 FETCH_ADVANCE_INST 1 # advance rPC, load rINST
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op_goto.S | 9 srl rINST, rINST, 8 10 seb rINST, rINST # rINST <- offset (sign-extended AA) 15 move a2, rINST 17 bnezc v0, MterpOnStackReplacement # Note: offset must be in rINST 19 dlsa rPC, rINST, rPC, 1 # rPC <- rPC + offset * 2 21 move a0, rINST # a0 <- offset 22 FETCH_INST # load rINST [all...] |
/art/runtime/interpreter/mterp/x86_64/ |
op_const_4.S | 3 movl $$0xf, rINST 4 andl %eax, rINST # rINST <- A
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op_array_length.S | 4 movl rINST, %eax # eax <- BA 5 sarl $$4, rINST # rINST <- B 10 movl MIRROR_ARRAY_LENGTH_OFFSET(%rcx), rINST 11 SET_VREG rINST, %rax
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binop2addr.S | 13 movl rINST, %ecx # rcx <- A+ 14 sarl $$4, rINST # rINST <- B
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binopWide2addr.S | 5 movl rINST, %ecx # rcx <- A+ 6 sarl $$4, rINST # rINST <- B
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op_move_wide.S | 3 movl rINST, %ecx # ecx <- BA 4 sarl $$4, rINST # rINST <- B
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/art/runtime/interpreter/mterp/mips/ |
op_goto_16.S | 9 FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended) 13 move a2, rINST 15 bnez v0, MterpOnStackReplacement # Note: offset must be in rINST 16 addu a1, rINST, rINST # a1 <- byte offset, flags set 17 FETCH_ADVANCE_INST_RB(a1) # update rPC, load rINST 22 GET_INST_OPCODE(t0) # extract opcode from rINST 25 FETCH_S(rINST, 1) # rINST <- ssssAAAA (sign-extended [all...] |