| /external/valgrind/none/tests/mips64/ |
| arithmetic_instruction.c | 31 TEST1("add $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
39 TEST2("addi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
40 TEST2("addi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
41 TEST2("addi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
42 TEST2("addi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
49 TEST2("addiu $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
50 TEST2("addiu $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
51 TEST2("addiu $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
52 TEST2("addiu $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1)
[all...] |
| shift_instructions.c | 24 TEST2("drotr $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
25 TEST2("drotr $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
26 TEST2("drotr $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
27 TEST2("drotr $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
37 TEST2("drotr32 $t0, $t1, 0x00", reg_val1[i], 0x00, t0, t1);
38 TEST2("drotr32 $t2, $t3, 0x1f", reg_val1[i], 0x1f, t2, t3);
39 TEST2("drotr32 $a0, $a1, 0x0f", reg_val1[i], 0x0f, a0, a1);
40 TEST2("drotr32 $s0, $s1, 0x03", reg_val1[i], 0x03, s0, s1);
50 TEST1("drotrv $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1]
[all...] |
| logical_instructions.c | 21 TEST1("and $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
30 TEST2("andi $t0, $t1, 0xff", reg_val1[i], 0xff, t0, t1);
31 TEST2("andi $t2, $t3, 0xffff", reg_val1[i], 0xffff, t2, t3);
32 TEST2("andi $a0, $a1, 0x0", reg_val1[i], 0x0, a0, a1);
33 TEST2("andi $s0, $s1, 0x23", reg_val1[i], 0x23, s0, s1);
54 TEST1("nor $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1],
62 TEST1("or $t0, $t1, $t2", reg_val1[i], reg_val1[N-i-1]
[all...] |
| load_store.c | 15 TEST1("lb", i, reg_val1);
22 TEST1("lbu", i, reg_val1);
29 TEST1("ld", i, reg_val1);
36 TEST1("ldl", i, reg_val1);
43 TEST1("ldr", i, reg_val1);
50 TEST1("lh", i, reg_val1);
57 TEST1("lhu", i, reg_val1);
64 TEST1("lw", i, reg_val1);
71 TEST1("lwl", i, reg_val1);
78 TEST1("lwr", i, reg_val1);
[all...] |
| fpu_load_store.c | 16 TEST3("ldc1", i, reg_val1);
23 TEST5("ldxc1", i, reg_val1);
30 TEST3w("lwc1", i, reg_val1);
37 TEST5w("lwxc1", i, reg_val1);
|
| branch_and_jump_instructions.c | 185 TEST1(reg_val1[i], t0);
189 TEST2(reg_val1[i], t0);
345 TEST2a(reg_val1[i], t0);
349 TEST2b(reg_val1[i], t1);
|
| macro_load_store.h | 97 : "r" (reg_val1) , "r" (reg_val_zero), "r" (offset) \
|
| const.h | 3 const int reg_val1[N] = { variable
|
| move_instructions.c | 203 TEST1(reg_val1[i]);
204 TEST2(reg_val1[i]);
|
