| /external/llvm/include/llvm/Target/ |
| TargetRegisterInfo.h | 243 typedef const TargetRegisterClass * const * regclass_iterator; typedef in class:llvm::TargetRegisterInfo
250 regclass_iterator RegClassBegin, RegClassEnd; // List of regclasses
255 regclass_iterator RegClassBegin,
256 regclass_iterator RegClassEnd,
602 regclass_iterator regclass_begin() const { return RegClassBegin; }
603 regclass_iterator regclass_end() const { return RegClassEnd; }
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetRegisterInfo.cpp | 31 regclass_iterator RCB, regclass_iterator RCE,
141 for (regclass_iterator I = regclass_begin(), E = regclass_end(); I != E; ++I){
171 for (TargetRegisterInfo::regclass_iterator I = regclass_begin(),
|
| RegisterClassInfo.cpp | 159 for (TargetRegisterInfo::regclass_iterator
|
| /external/llvm/include/llvm/MC/ |
| MCRegisterInfo.h | 137 typedef const MCRegisterClass *regclass_iterator; typedef in class:llvm::MCRegisterInfo
399 regclass_iterator regclass_begin() const { return Classes; }
400 regclass_iterator regclass_end() const { return Classes+NumClasses; }
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 60 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
367 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
374 for (TargetRegisterInfo::regclass_iterator I = TRI->regclass_begin(),
|
| ScheduleDAGRRList.cpp | [all...] |
| TargetLowering.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 135 for (regclass_iterator I = regclass_begin(), E = regclass_end();
|
