/toolchain/binutils/binutils-2.25/gas/testsuite/gas/rx/ |
rotr.d | 9 0: fd 6c 00 rotr #0, r0 10 3: fd 6c 0f rotr #0, r15 11 6: fd 6d f0 rotr #31, r0 12 9: fd 6d ff rotr #31, r15 13 c: fd 64 00 rotr r0, r0 14 f: fd 64 0f rotr r0, r15 15 12: fd 64 f0 rotr r15, r0 16 15: fd 64 ff rotr r15, r15
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/external/llvm/test/MC/Mips/ |
set-mips0-directive.s | 5 rotr $7, $7, 22 10 rotr $2, $2, 15 15 rotr $3, $3, 19 17 # CHECK: rotr $7, $7, 22 22 # CHECK: rotr $2, $2, 15 27 # CHECK: rotr $3, $3, 19
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set-mips-directives.s | 19 rotr $2,15 22 rotr $2,15 25 rotr $2,15 55 # CHECK: rotr $2, $2, 15 58 # CHECK: rotr $2, $2, 15 61 # CHECK: rotr $2, $2, 15
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rotations32.s | 25 # CHECK-32R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02] 28 # CHECK-32R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02] 33 # CHECK-32R: rotr $4, $4, 31 # encoding: [0x00,0x24,0x27,0xc2] 38 # CHECK-32R: rotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xc2] 43 # CHECK-32R: rotr $4, $4, 30 # encoding: [0x00,0x24,0x27,0x82] 48 # CHECK-32R: rotr $4, $5, 30 # encoding: [0x00,0x25,0x27,0x82] 64 # CHECK-32R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02] 67 # CHECK-32R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02] 72 # CHECK-32R: rotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x42] 77 # CHECK-32R: rotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x42 [all...] |
set-arch.s | 18 rotr $2, $2, 15 21 rotr $2, $2, 15 24 rotr $2, $2, 15 56 # CHECK: rotr $2, $2, 15
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micromips-shift-instructions.s | 16 # CHECK-EL: rotr $9, $6, 7 # encoding: [0x26,0x01,0xc0,0x38] 27 # CHECK-EB: rotr $9, $6, 7 # encoding: [0x01,0x26,0x38,0xc0] 35 rotr $9, $6, 7
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rotations64.s | 25 # CHECK-64R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02] 28 # CHECK-64R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02] 33 # CHECK-64R: rotr $4, $4, 31 # encoding: [0x00,0x24,0x27,0xc2] 38 # CHECK-64R: rotr $4, $5, 31 # encoding: [0x00,0x25,0x27,0xc2] 43 # CHECK-64R: rotr $4, $4, 30 # encoding: [0x00,0x24,0x27,0x82] 48 # CHECK-64R: rotr $4, $5, 30 # encoding: [0x00,0x25,0x27,0x82] 64 # CHECK-64R: rotr $4, $4, 0 # encoding: [0x00,0x24,0x20,0x02] 67 # CHECK-64R: rotr $4, $5, 0 # encoding: [0x00,0x25,0x20,0x02] 72 # CHECK-64R: rotr $4, $4, 1 # encoding: [0x00,0x24,0x20,0x42] 77 # CHECK-64R: rotr $4, $5, 1 # encoding: [0x00,0x25,0x20,0x42 [all...] |
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
rotX.s | 2 .rotr a[8], b[-8]
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nostkreg.s | 5 .rotr in0I[2], loc1L[2], out2O[2]
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pound.s | 25 .rotr r#[2], r1#[4]
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index.s | 35 .rotr reg[8]
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
smartmips.s | 7 rotr $4,$5,$6 14 rotr $4,$5,31
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mips32r2.s | 36 rotr $25, $10, 4 38 rotr $25, $10, $4
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/h8300/ |
rotsh.s | 4 rotr r0l
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rotshh.s | 7 rotr.b r0l 8 rotr.w r0 9 rotr.l er0
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rotshs.s | 10 rotr.b r0l 11 rotr.b #2,r0l 12 rotr.w r0 13 rotr.w #2,r0 14 rotr.l er0 15 rotr.l #2,er0
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t11_logs.s | [all...] |
/external/wpa_supplicant_8/src/crypto/ |
aes_i.h | 70 static inline u32 rotr(u32 val, int bits) function 76 #define TE1(i) rotr(Te0[((i) >> 16) & 0xff], 8) 77 #define TE2(i) rotr(Te0[((i) >> 8) & 0xff], 16) 78 #define TE3(i) rotr(Te0[(i) & 0xff], 24) 94 #define TD1(i) rotr(Td0[((i) >> 16) & 0xff], 8) 95 #define TD2(i) rotr(Td0[((i) >> 8) & 0xff], 16) 96 #define TD3(i) rotr(Td0[(i) & 0xff], 24) 102 #define TD1_(i) rotr(Td0[(i) & 0xff], 8) 103 #define TD2_(i) rotr(Td0[(i) & 0xff], 16) 104 #define TD3_(i) rotr(Td0[(i) & 0xff], 24 [all...] |
/external/skia/bench/ |
FontCacheBench.cpp | 56 static uint32_t rotr(uint32_t value, unsigned bits) { function 103 if (false) rotr(0, 0);
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/external/llvm/test/MC/Mips/mips64/ |
invalid-mips64r2.s | 20 rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 21 rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/toolchain/binutils/binutils-2.25/gas/testsuite/gas/nds32/ |
alu-1.s | 9 rotr $r0, $r1, $r2
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/external/llvm/test/MC/Mips/mips32/ |
invalid-mips32r2.s | 28 rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 29 rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/llvm/test/MC/Mips/mips5/ |
invalid-mips64r2.s | 34 rotr $1,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled 35 rotr $1,$14,15 # CHECK: :[[@LINE]]:{{[0-9]+}}: error: instruction requires a CPU feature not currently enabled
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/external/boringssl/src/crypto/perlasm/ |
cbc.pl | 283 &rotr("edx", 16); 294 &rotr("ecx", 16);
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/external/llvm/test/MC/Mips/micromips/ |
invalid.s | 27 rotr $2, $3, 32 # CHECK: :[[@LINE]]:16: error: expected 5-bit unsigned immediate
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