| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| sb1-ext-mdmx.s | 14 movf.l $v1, $v12, $fcc5
16 movn.l $v1, $v12, $18
18 movt.l $v1, $v12, $fcc5
20 movz.l $v1, $v12, $18
22 add.ob $v1, $v12, 18
23 add.ob $v1, $v12, $v18
24 add.ob $v1, $v12, $v18[6]
26 adda.ob $v12, 18
27 adda.ob $v12, $v18
28 adda.ob $v12, $v18[6
[all...] |
| sb1-ext-mdmx.d | 14 0+0010 <[^>]*> 7bd2604b add\.ob \$v1,\$v12,0x12
15 0+0014 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
16 0+0018 <[^>]*> 7992604b add\.ob \$v1,\$v12,\$v18\[6\]
17 0+001c <[^>]*> 7bd26037 adda\.ob \$v12,0x12
18 0+0020 <[^>]*> 7ad26037 adda\.ob \$v12,\$v18
19 0+0024 <[^>]*> 79926037 adda\.ob \$v12,\$v18\[6\]
20 0+0028 <[^>]*> 7bd26437 addl\.ob \$v12,0x12
21 0+002c <[^>]*> 7ad26437 addl\.ob \$v12,\$v18
22 0+0030 <[^>]*> 79926437 addl\.ob \$v12,\$v18\[6\]
23 0+0034 <[^>]*> 78d26058 alni\.ob \$v1,\$v12,\$v18,
[all...] |
| mips64-mdmx.s | 9 movf.l $v1, $v12, $fcc5
11 movn.l $v1, $v12, $18
13 movt.l $v1, $v12, $fcc5
15 movz.l $v1, $v12, $18
17 add.ob $v1, $v12, 18
18 add.ob $v1, $v12, $v18
19 add.ob $v1, $v12, $v18[6]
21 add.qh $v1, $v12, 18
22 add.qh $v1, $v12, $v18
23 add.qh $v1, $v12, $v18[2
[all...] |
| mips64-mdmx.d | 14 0+0010 <[^>]*> 7bd2604b add\.ob \$v1,\$v12,0x12
15 0+0014 <[^>]*> 7ad2604b add\.ob \$v1,\$v12,\$v18
16 0+0018 <[^>]*> 7992604b add\.ob \$v1,\$v12,\$v18\[6\]
17 0+001c <[^>]*> 7bb2604b add\.qh \$v1,\$v12,0x12
18 0+0020 <[^>]*> 7ab2604b add\.qh \$v1,\$v12,\$v18
19 0+0024 <[^>]*> 7932604b add\.qh \$v1,\$v12,\$v18\[2\]
20 0+0028 <[^>]*> 7bd26037 adda\.ob \$v12,0x12
21 0+002c <[^>]*> 7ad26037 adda\.ob \$v12,\$v18
22 0+0030 <[^>]*> 79926037 adda\.ob \$v12,\$v18\[6\]
23 0+0034 <[^>]*> 7bb26037 adda\.qh \$v12,0x1
[all...] |
| /external/llvm/test/MC/AArch64/ |
| noneon-diagnostics.s | 4 fmla v3.4s, v12.4s, v17.4s
8 // CHECK-ERROR-NEXT: fmla v3.4s, v12.4s, v17.4s
17 fmls v3.4s, v12.4s, v17.4s
22 // CHECK-ERROR-NEXT: fmls v3.4s, v12.4s, v17.4s
32 fmls.4s v3, v12, v17
37 // CHECK-ERROR-NEXT: fmls.4s v3, v12, v17
|
| neon-facge-facgt.s | 35 facgt v3.4h, v8.4h, v12.4h
38 facgt v3.2s, v8.2s, v12.2s
40 faclt v3.4h, v12.4h, v8.4h
43 faclt v3.2s, v12.2s, v8.2s
46 // CHECK: facgt v3.4h, v8.4h, v12.4h // encoding: [0x03,0x2d,0xcc,0x2e]
49 // CHECK: facgt v3.2s, v8.2s, v12.2s // encoding: [0x03,0xed,0xac,0x2e]
51 // CHECK: facgt v3.4h, v8.4h, v12.4h // encoding: [0x03,0x2d,0xcc,0x2e]
54 // CHECK: facgt v3.2s, v8.2s, v12.2s // encoding: [0x03,0xed,0xac,0x2e]
|
| neon-frsqrt-frecp.s | 23 frecps v3.4h, v8.4h, v12.4h
26 frecps v3.2s, v8.2s, v12.2s
29 // CHECK: frecps v3.4h, v8.4h, v12.4h // encoding: [0x03,0x3d,0x4c,0x0e]
32 // CHECK: frecps v3.2s, v8.2s, v12.2s // encoding: [0x03,0xfd,0x2c,0x0e]
|
| /toolchain/binutils/binutils-2.25/gold/testsuite/ |
| tls_test.cc | 82 static __thread struct int128 v12 = { 115, 125 }; variable in typeref:struct:int128
201 CHECK_EQ_OR_RETURN((int) v12.hi, 115);
202 CHECK_EQ_OR_RETURN((int) v12.lo, 125);
203 v12 = newval;
216 CHECK_EQ_OR_RETURN((int) v12.hi, 335);
217 CHECK_EQ_OR_RETURN((int) v12.lo, 345);
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_ColorMatrix.S | 80 vmxx_s16 \i, 1, v6.4s, v12.4h, v0.h[0]
84 vmxx2_s16 \i, 1, v7.4s, v12.8h, v0.h[0]
97 vmxx_s16 \i^31, 1, v6.4s, v12.4h, v0.h[0]
101 vmxx2_s16 \i^31, 1, v7.4s, v12.8h, v0.h[0]
115 vmxx_s16 \i, 1, v6.4s, v12.4h, v0.h[1]
119 vmxx2_s16 \i, 1, v7.4s, v12.8h, v0.h[1]
132 vmxx_s16 \i^31, 1, v6.4s, v12.4h, v0.h[1]
136 vmxx2_s16 \i^31, 1, v7.4s, v12.8h, v0.h[1]
150 vmxx_s16 \i, 1, v6.4s, v12.4h, v0.h[2]
154 vmxx2_s16 \i, 1, v7.4s, v12.8h, v0.h[2
[all...] |
| rsCpuIntrinsics_advsimd_Resize.S | 42 * v12. This gives eight 16-bit results representing a horizontal line of 2-8
49 * v12. This gives eight 16-bit results.
51 .macro vert8, dstlo=v12.4h, dsthi=v12.8h
60 umull v12.4s, v9.4h, v3.h[1]
62 umlsl v12.4s, v8.4h, v3.h[0]
64 umlal v12.4s, v10.4h, v3.h[2]
66 umlsl v12.4s, v11.4h, v3.h[3]
73 sqshrn \dstlo, v12.4s, #8 + (16 - VERTBITS)
79 .macro vert4, dst=v12.8
[all...] |
| rsCpuIntrinsics_advsimd_Blur.S | 80 * v12-v15 = temporary sums
98 umull v12.4s, v14.4h, v0.h[0]
121 umlal v12.4s, v16.4h, \dreg
147 umlal v12.4s, v16.4h, \dreg
228 2: uqrshrn v10.4h, v12.4s, #16 - FRACTION_BITS
260 * v12-v13 -- temporaries for load and vext operations.
286 107: ext v12.16b, v8.16b, v9.16b, #1*2
288 umlal v14.4s, v12.4h, v0.h[7]
289 umlal2 v15.4s, v12.8h, v0.h[7]
292 106: ext v12.16b, v8.16b, v9.16b, #2*
[all...] |
| rsCpuIntrinsics_advsimd_Convolve.S | 33 st1 {v12.1d-v15.1d}, [x6]
97 ld1 {v12.1d-v15.1d}, [sp], #32
118 st1 {v12.1d-v15.1d}, [x8]
132 ld1 {v12.8b-v14.8b}, [x2], x6 // y0 ( y - 1 )
142 uxtl v12.8h, v12.8b
148 v12, v12hi
161 smlal v4.4s, v12.4h, v0.h[5]
162 smlal2 v5.4s, v12.8h, v0.h[5]
163 smlal2 v4.4s, v12.8h, v0.h[6
[all...] |
| /cts/tools/vm-tests-tf/src/dot/junit/opcodes/neg_long/d/ |
| T_neg_long_2.d | 16 neg-long v10, v12
18 not-long v8, v12
|
| /cts/tools/vm-tests-tf/src/dot/junit/opcodes/rem_double_2addr/d/ |
| T_rem_double_2addr_2.d | 16 rem-double/2addr v12, v14
17 return-wide v12
|
| T_rem_double_2addr_1.d | 16 rem-double/2addr v10, v12
|
| /external/libavc/common/armv8/ |
| ih264_weighted_bi_pred_av8.s | 201 ld1 {v12.8b}, [x0], x3 //load row 3 in source 1
210 uxtl v12.8h, v12.8b //converting row 3 in source 1 to 16-bit
216 mul v12.8h, v12.8h , v2.h[0] //weight 1 mult. for row 3
217 mla v12.8h, v14.8h , v2.h[2] //weight 2 mult. for row 3
222 srshl v12.8h, v12.8h , v0.8h //rounds off the weighted samples from row 3
226 saddw v12.8h, v12.8h , v3.8b //adding offset for row
[all...] |
| ih264_inter_pred_luma_horz_qpel_vert_qpel_av8.s | 183 ld1 {v12.2s, v13.2s}, [x7], x2 // src[6_0]
191 uaddl v16.8h, v2.8b, v12.8b
244 umlsl v16.8h, v12.8b, v31.8b
289 umlal v0.8h, v12.8b, v30.8b
341 mov v4.16b, v12.16b
387 ld1 {v12.2s, v13.2s}, [x7], x2 // src[10_0]
393 uaddl v16.8h, v2.8b, v12.8b
444 umlsl v16.8h, v12.8b, v31.8b
489 umlal v0.8h, v12.8b, v30.8b
541 mov v4.16b, v12.16
[all...] |
| ih264_inter_pred_filters_luma_vert_av8.s | 131 uaddl v12.8h, v4.8b, v6.8b // temp1 = src[2_0] + src[3_0]
138 mla v14.8h, v12.8h, v22.8h // temp += temp1 * 20
144 uaddl v12.8h, v6.8b, v8.8b
148 mla v16.8h, v12.8h , v22.8h
151 uaddl v12.8h, v7.8b, v9.8b
155 mla v14.8h, v12.8h , v22.8h
159 uaddl v12.8h, v8.8b, v10.8b
162 mla v18.8h, v12.8h , v22.8h
166 uaddl v12.8h, v9.8b, v11.8b
169 mla v16.8h, v12.8h , v22.8
[all...] |
| ih264_inter_pred_luma_vert_qpel_av8.s | 138 uaddl v12.8h, v4.8b, v6.8b // temp1 = src[2_0] + src[3_0]
145 mla v14.8h, v12.8h , v22.8h // temp += temp1 * 20
151 uaddl v12.8h, v6.8b, v8.8b
155 mla v16.8h, v12.8h , v22.8h
158 uaddl v12.8h, v7.8b, v9.8b
162 mla v14.8h, v12.8h , v22.8h
169 uaddl v12.8h, v8.8b, v10.8b
171 mla v18.8h, v12.8h , v22.8h
175 uaddl v12.8h, v9.8b, v11.8b
178 mla v16.8h, v12.8h , v22.8
[all...] |
| ih264_inter_pred_luma_horz_hpel_vert_hpel_av8.s | 95 ld1 {v12.2s}, [x0], x2 // Vector load from src[0_0]
120 uaddl v22.8h, v12.8b, v17.8b
183 ld1 {v12.2s}, [x0], x2 // Vector load from src[6_0]
201 uaddl v22.8h, v13.8b, v12.8b
282 uaddl v26.8h, v15.8b, v12.8b
360 uaddl v24.8h, v17.8b, v12.8b
424 mov v14.16b, v12.16b
440 mov v12.16b, v16.16b
463 uaddl v12.8h, v0.8b, v10.8b
465 mla v12.8h, v14.8h , v26.8
[all...] |
| /external/libhevc/common/arm64/ |
| ihevc_intra_pred_chroma_planar.s | 187 umull v12.8h, v5.8b, v0.8b //(row+1) * src[nt-1]
190 umlal v12.8h, v6.8b, v10.8b //(nt-1-row) * src[2nt+1+col]
192 umlal v12.8h, v17.8b, v1.8b //(col+1) * src[3nt+1]
194 umlal v12.8h, v30.8b, v4.8b //(nt-1-col) * src[2nt-1-row]
211 add v12.8h, v12.8h , v16.8h //add (nt)
213 sshl v12.8h, v12.8h, v14.8h //shr
228 xtn v12.8b, v12.8
[all...] |
| ihevc_itrans_recon_32x32.s | 245 ld1 {v12.4h},[x0],x6
268 smlal v20.4s, v12.4h, v1.h[0]
270 smlal v22.4s, v12.4h, v3.h[0]
272 smlal v16.4s, v12.4h, v5.h[0]
274 smlal v18.4s, v12.4h, v7.h[0]
317 ld1 {v12.4h},[x0],x6
342 smlal v20.4s, v12.4h, v3.h[0]
344 smlsl v22.4s, v12.4h, v7.h[0]
346 smlsl v16.4s, v12.4h, v1.h[0]
348 smlsl v18.4s, v12.4h, v5.h[0
[all...] |
| /external/libjpeg-turbo/simd/ |
| jsimd_arm64_neon.S | 263 st1 {v12.8b, v13.8b, v14.8b, v15.8b}, [sp], 32
306 st1 {v12.4h, v13.4h, v14.4h, v15.4h}, [sp], 32
310 smull v12.4s, v4.4h, XFIX_1_175875602_MINUS_1_961570560
311 smlal v12.4s, v5.4h, XFIX_1_175875602
320 mov v8.16b, v12.16b
321 smlsl v12.4s, ROW5L.4h, XFIX_2_562915447
323 smlal v12.4s, ROW3L.4h, XFIX_3_072711026_MINUS_2_562915447
331 add v2.4s, v2.4s, v12.4s
338 sub v2.4s, v2.4s, v12.4s
343 sub v2.4s, v2.4s, v12.4
[all...] |
| /external/clang/test/CodeGen/ |
| vector-alignment.c | 60 double __attribute__((vector_size(80), aligned(16))) v12; variable
61 // ALL: @v12 {{.*}}, align 16
|
| /cts/tools/vm-tests-tf/src/dot/junit/opcodes/rem_double/d/ |
| T_rem_double_5.d | 16 rem-double v0, v9, v12
|
