| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 135 { ISD::SHL, MVT::v16i32, 1 },
136 { ISD::SRL, MVT::v16i32, 1 },
137 { ISD::SRA, MVT::v16i32, 1 },
555 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 1 },
556 { ISD::TRUNCATE, MVT::v16i16, MVT::v16i32, 1 },
560 // v16i1 -> v16i32 - load + broadcast
561 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
562 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i1, 2 },
564 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 1 },
565 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 1 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 91 v16i32 = 42, // 16 x i32 enumerator in enum:llvm::MVT::SimpleValueType
259 SimpleTy == MVT::v32i16 || SimpleTy == MVT::v16i32 ||
339 case v16i32:
385 case v16i32:
492 case v16i32:
621 if (NumElements == 16) return MVT::v16i32;
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 194 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
211 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
212 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
393 { ISD::SELECT, MVT::v16i1, MVT::v16i32, 16 },
|
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 95 { ISD::SIGN_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
96 { ISD::ZERO_EXTEND, MVT::v16i32, MVT::v16i8, 6 },
99 { ISD::TRUNCATE, MVT::v16i8, MVT::v16i32, 6 },
124 { ISD::SINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
125 { ISD::UINT_TO_FP, MVT::v16f32, MVT::v16i32, 4 },
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 169 case MVT::v16i32: return "v16i32";
247 case MVT::v16i32: return VectorType::get(Type::getInt32Ty(Context), 16);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 197 if (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
337 (LocVT == MVT::v8i64 || LocVT == MVT::v16i32 || LocVT == MVT::v32i16 ||
410 LocVT == MVT::v16i32 || LocVT == MVT::v8i64 ||
412 LocVT = MVT::v16i32;
413 ValVT = MVT::v16i32;
436 if (LocVT == MVT::v16i32 || LocVT == MVT::v32i32 || LocVT == MVT::v64i32) {
483 if (LocVT == MVT::v16i32) {
544 return (ty == MVT::v8i64 || ty == MVT::v16i32 || ty == MVT::v32i16 ||
[all...] |
| HexagonISelDAGToDAG.cpp | 405 } else if (LoadedVT == MVT::v16i32 || LoadedVT == MVT::v8i64 ||
526 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
568 else if (StoredVT == MVT::v16i32 || StoredVT == MVT::v8i64 ||
[all...] |
| HexagonInstrInfo.cpp | [all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIISelLowering.cpp | 64 addRegisterClass(MVT::v16i32, &AMDGPU::SReg_512RegClass);
71 setOperationAction(ISD::VECTOR_SHUFFLE, MVT::v16i32, Expand);
89 setOperationAction(ISD::LOAD, MVT::v16i32, Custom);
92 setOperationAction(ISD::STORE, MVT::v16i32, Custom);
168 setTruncStoreAction(MVT::v16i32, MVT::v16i8, Expand);
169 setTruncStoreAction(MVT::v16i32, MVT::v16i16, Expand);
205 for (MVT VT : {MVT::v8i32, MVT::v8f32, MVT::v16i32, MVT::v16f32, MVT::v2i64, MVT::v2f64}) {
[all...] |
| AMDGPUISelLowering.cpp | 123 AddPromotedToType(ISD::STORE, MVT::v16f32, MVT::v16i32);
163 AddPromotedToType(ISD::LOAD, MVT::v16f32, MVT::v16i32);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 102 case MVT::v16i32: return "MVT::v16i32";
|
