| /external/clang/test/CodeGen/ |
| vectorcall.c | 56 typedef float __attribute__((vector_size(16))) v4f32; typedef
57 struct HVA2 { v4f32 x, y; };
58 struct HVA4 { v4f32 w, x, y, z; };
64 void __vectorcall hva2(struct HVA4 a, struct HVA4 b, v4f32 c) {}
68 void __vectorcall hva3(v4f32 a, v4f32 b, v4f32 c, v4f32 d, v4f32 e, struct HVA2 f) {}
|
| x86_64-arguments.c | 159 typedef float v4f32 __attribute__((__vector_size__(16))); typedef
160 v4f32 f25(v4f32 X) {
183 v4f32 v;
|
| systemz-abi-vector.c | 32 typedef __attribute__((vector_size(16))) float v4f32; typedef
114 v4f32 pass_v4f32(v4f32 arg) { return arg; }
[all...] |
| builtins-mips-msa.c | 14 typedef float v4f32 __attribute__ ((vector_size(16))); typedef
47 v4f32 v4f32_a = (v4f32) {0.5, 1, 2, 3};
48 v4f32 v4f32_b = (v4f32) {1.5, 2, 3, 4};
49 v4f32 v4f32_r;
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 216 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
219 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
230 // Complex: to v4f32
231 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 4 },
232 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
233 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
234 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
257 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 },
260 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
271 // Complex, from v4f32: legal type is v4i16, 1 narrowing => ~
[all...] |
| AArch64ISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 59 { ISD::FP_EXTEND, MVT::v4f32, 4 }
103 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
104 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
112 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
113 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 },
114 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
115 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i8, 3 },
116 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
117 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i16, 2 },
127 { ISD::FP_TO_SINT, MVT::v4i32, MVT::v4f32, 1 }
[all...] |
| ARMISelLowering.cpp | 473 addQRTypeForNEON(MVT::v4f32);
482 // The same with v4f32. But keep in mind that vadd, vsub, vmul are natively
483 // supported for v4f32.
519 setOperationAction(ISD::FSQRT, MVT::v4f32, Expand);
520 setOperationAction(ISD::FSIN, MVT::v4f32, Expand);
521 setOperationAction(ISD::FCOS, MVT::v4f32, Expand);
522 setOperationAction(ISD::FPOWI, MVT::v4f32, Expand);
523 setOperationAction(ISD::FPOW, MVT::v4f32, Expand);
524 setOperationAction(ISD::FLOG, MVT::v4f32, Expand);
525 setOperationAction(ISD::FLOG2, MVT::v4f32, Expand)
[all...] |
| ARMISelDAGToDAG.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 432 // 64-bit packed float vectors (v2f32) are widened to type v4f32.
468 // nodes. A v4i32/v4f32 BLENDI generates a single 'blendps'/'blendpd'.
470 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 1},
492 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2},
508 {ISD::VECTOR_SHUFFLE, MVT::v4f32, 2}, // shufps + pshufd
539 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i64, 1 },
546 { ISD::FP_TO_UINT, MVT::v4i64, MVT::v4f32, 1 },
587 { ISD::UINT_TO_FP, MVT::v4f32, MVT::v4i32, 1 },
605 { ISD::FP_TO_UINT, MVT::v4i32, MVT::v4f32, 1 },
671 { ISD::SINT_TO_FP, MVT::v4f32, MVT::v4i1, 3 }
[all...] |
| X86ISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineValueType.h | 112 v4f32 = 57, // 4 x f32 enumerator in enum:llvm::MVT::SimpleValueType
245 SimpleTy == MVT::v4f32 || SimpleTy == MVT::v2f64);
354 case v4f32:
402 case v4f32:
481 case v4f32:
644 if (NumElements == 4) return MVT::v4f32;
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 513 setOperationAction(ISD::FFLOOR, MVT::v4f32, Legal);
514 setOperationAction(ISD::FCEIL, MVT::v4f32, Legal);
515 setOperationAction(ISD::FTRUNC, MVT::v4f32, Legal);
516 setOperationAction(ISD::FNEARBYINT, MVT::v4f32, Legal);
518 addRegisterClass(MVT::v4f32, &PPC::VRRCRegClass);
523 setOperationAction(ISD::MUL, MVT::v4f32, Legal);
524 setOperationAction(ISD::FMA, MVT::v4f32, Legal);
527 setOperationAction(ISD::FDIV, MVT::v4f32, Legal);
528 setOperationAction(ISD::FSQRT, MVT::v4f32, Legal);
539 setOperationAction(ISD::SCALAR_TO_VECTOR, MVT::v4f32, Custom)
[all...] |
| PPCTargetTransformInfo.cpp | 349 LT.second == MVT::v4i32 || LT.second == MVT::v4f32);
353 (LT.second == MVT::v4f64 || LT.second == MVT::v4f32);
|
| /external/llvm/lib/IR/ |
| ValueTypes.cpp | 184 case MVT::v4f32: return "v4f32";
262 case MVT::v4f32: return VectorType::get(Type::getFloatTy(Context), 4);
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| R600GenRegisterInfo.pl | 97 def R600_Reg128 : RegisterClass<"AMDGPU", [v4f32, v4i32], 128, (add
|
| AMDILISelLowering.cpp | 61 (int)MVT::v4f32,
89 (int)MVT::v4f32,
505 FLTTY = MVT::v4f32;
|
| R600ISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
|
| SIISelLowering.cpp | 30 addRegisterClass(MVT::v4f32, &AMDGPU::VReg_128RegClass);
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 211 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
284 else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUISelLowering.cpp | 116 setOperationAction(ISD::STORE, MVT::v4f32, Promote);
117 AddPromotedToType(ISD::STORE, MVT::v4f32, MVT::v4i32);
156 setOperationAction(ISD::LOAD, MVT::v4f32, Promote);
157 AddPromotedToType(ISD::LOAD, MVT::v4f32, MVT::v4i32);
172 setOperationAction(ISD::CONCAT_VECTORS, MVT::v4f32, Custom);
177 setOperationAction(ISD::EXTRACT_SUBVECTOR, MVT::v4f32, Custom);
224 setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
234 setTruncStoreAction(MVT::v4f32, MVT::v4f16, Expand);
337 MVT::v2f32, MVT::v4f32
[all...] |
| R600ISelLowering.cpp | 36 addRegisterClass(MVT::v4f32, &AMDGPU::R600_Reg128RegClass);
161 setOperationAction(ISD::EXTRACT_VECTOR_ELT, MVT::v4f32, Custom);
166 setOperationAction(ISD::INSERT_VECTOR_ELT, MVT::v4f32, Custom);
670 MVT::v4f32, DAG.getTargetConstant(slot / 4, DL, MVT::i32));
785 return DAG.getNode(AMDGPUISD::TEXTURE_FETCH, DL, MVT::v4f32, TexArgs);
[all...] |
| /external/llvm/utils/TableGen/ |
| CodeGenTarget.cpp | 117 case MVT::v4f32: return "MVT::v4f32";
|
| /prebuilts/gcc/darwin-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 47 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
|
| /prebuilts/gcc/linux-x86/mips/mips64el-linux-android-4.9/lib/gcc/mips64el-linux-android/4.9/include/ |
| msa.h | 47 typedef float v4f32 __attribute__((vector_size(16), aligned(16))); typedef
|
