| /external/llvm/lib/Target/AMDGPU/ |
| SILowerControlFlow.cpp | 413 const TargetRegisterClass *RC = TRI->getPhysRegClass(SubReg);
423 Reg = RC->getRegister(RegIdx);
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| SIRegisterInfo.cpp | 137 const TargetRegisterClass *RC = *I;
139 unsigned NumSubRegs = std::max((int)RC->getSize() / 4, 1);
142 if (isPseudoRegClass(RC)) {
146 } else if (isSGPRClass(RC)) {
152 const int *Sets = getRegClassPressureSets(RC);
427 bool SIRegisterInfo::hasVGPRs(const TargetRegisterClass *RC) const {
428 switch (RC->getSize()) {
430 return getCommonSubClass(&AMDGPU::VGPR_32RegClass, RC) != nullptr;
432 return getCommonSubClass(&AMDGPU::VReg_64RegClass, RC) != nullptr;
434 return getCommonSubClass(&AMDGPU::VReg_96RegClass, RC) != nullptr
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16ISelDAGToDAG.cpp | 78 const TargetRegisterClass *RC = &Mips::CPU16RegsRegClass;
80 V0 = RegInfo.createVirtualRegister(RC);
81 V1 = RegInfo.createVirtualRegister(RC);
82 V2 = RegInfo.createVirtualRegister(RC);
|
| MipsOptimizePICCall.cpp | 119 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(Reg);
120 assert(RC->vt_end() - RC->vt_begin() == 1);
121 return *RC->vt_begin();
|
| MipsSEInstrInfo.cpp | 182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
189 if (Mips::GPR32RegClass.hasSubClassEq(RC))
191 else if (Mips::GPR64RegClass.hasSubClassEq(RC))
193 else if (Mips::ACC64RegClass.hasSubClassEq(RC))
195 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
197 else if (Mips::ACC128RegClass.hasSubClassEq(RC))
199 else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
201 else if (Mips::FGR32RegClass.hasSubClassEq(RC))
203 else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
205 else if (Mips::FGR64RegClass.hasSubClassEq(RC))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 217 unsigned RC;
218 bool HasRC = InlineAsm::hasRegClassConstraint(Flag, RC);
219 if ((!IsTiedToChangedOp && (!HasRC || RC != SP::IntRegsRegClassID))
|
| /external/llvm/lib/Target/X86/ |
| X86VZeroUpper.cpp | 264 const TargetRegisterClass *RC = &X86::VR256RegClass;
265 for (TargetRegisterClass::iterator i = RC->begin(), e = RC->end(); i != e;
|
| /external/harfbuzz_ng/src/ |
| hb-ot-shape-complex-thai.cc | 40 RC,
52 return RC;
173 T0, /* RC */
200 B1, /* RC */
|
| /external/llvm/lib/CodeGen/ |
| MachineCSE.cpp | 145 // RC = TRI->getMatchingSuperRegClass(MRI->getRegClass(SrcReg), RC,
155 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
156 if (!MRI->constrainRegClass(SrcReg, RC))
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| PHIElimination.cpp | 263 const TargetRegisterClass *RC = MF.getRegInfo().getRegClass(DestReg);
264 entry = IncomingReg = MF.getRegInfo().createVirtualRegister(RC);
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| PrologEpilogInserter.cpp | 329 const TargetRegisterClass *RC = RegInfo->getMinimalPhysRegClass(Reg);
346 unsigned Align = RC->getAlignment();
353 FrameIdx = MFI->CreateStackObject(RC->getSize(), Align, true);
359 MFI->CreateFixedSpillStackObject(RC->getSize(), FixedSlot->Offset);
453 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
455 RC, TRI);
482 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
483 TII.loadRegFromStackSlot(*MBB, I, Reg, CSI[i].getFrameIdx(), RC, TRI);
[all...] |
| RegAllocFast.cpp | 167 int getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC);
201 int RAFast::getStackSpaceFor(unsigned VirtReg, const TargetRegisterClass *RC) {
208 int FrameIdx = MF->getFrameInfo()->CreateSpillStackObject(RC->getSize(),
209 RC->getAlignment());
287 const TargetRegisterClass *RC = MRI->getRegClass(LRI->VirtReg);
288 int FI = getStackSpaceFor(LRI->VirtReg, RC);
290 TII->storeRegToStackSlot(*MBB, MI, LR.PhysReg, SpillKill, FI, RC, TRI);
523 const TargetRegisterClass *RC = MRI->getRegClass(VirtReg);
527 !RC->contains(Hint) || !MRI->isAllocatable(Hint)))
543 ArrayRef<MCPhysReg> AO = RegClassInfo.getOrder(RC);
[all...] |
| RegAllocPBQP.cpp | 708 const TargetRegisterClass &RC = *MRI.getRegClass(LI.reg);
709 PReg = RC.getRawAllocationOrder(MF).front();
|
| TailDuplication.cpp | 403 const TargetRegisterClass *RC = MRI->getRegClass(DefReg);
408 unsigned NewDef = MRI->createVirtualRegister(RC);
440 const TargetRegisterClass *RC = MRI->getRegClass(Reg);
441 unsigned NewReg = MRI->createVirtualRegister(RC);
[all...] |
| TargetLoweringBase.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitTracker.cpp | 82 const TargetRegisterClass *RC = MRI.getRegClass(Reg);
83 unsigned ID = RC->getID();
179 #define rc(i) RegisterCell::ref(getCell(Reg[i],Inputs)) macro
201 return rc(N);
204 auto lo = [this] (const BT::RegisterCell &RC, uint16_t RW)
206 assert(RW <= RC.width());
207 return eXTR(RC, 0, RW);
210 auto hi = [this] (const BT::RegisterCell &RC, uint16_t RW)
212 uint16_t W = RC.width();
214 return eXTR(RC, W-RW, W)
877 #undef rc macro
[all...] |
| HexagonGenPredicate.cpp | 115 const TargetRegisterClass *RC = MRI->getRegClass(R);
116 return RC == &Hexagon::PredRegsRegClass;
417 const TargetRegisterClass *RC = MRI->getRegClass(OutR.R);
418 unsigned NewOutR = MRI->createVirtualRegister(RC);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCRegisterInfo.cpp | 256 unsigned PPCRegisterInfo::getRegPressureLimit(const TargetRegisterClass *RC,
261 switch (RC->getID()) {
291 PPCRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
298 if (RC == &PPC::F8RCRegClass)
300 else if (RC == &PPC::VRRCRegClass)
302 else if (RC == &PPC::F4RCRegClass && Subtarget.hasP8Vector())
306 return TargetRegisterInfo::getLargestLegalSuperClass(RC, MF);
859 const TargetRegisterClass *RC = is64Bit ? G8RC : GPRC;
860 unsigned SRegHi = MF.getRegInfo().createVirtualRegister(RC),
861 SReg = MF.getRegInfo().createVirtualRegister(RC);
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 439 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
440 TII.storeRegToStackSlot(MBB, MI, Reg, true, it->getFrameIdx(), RC, TRI);
467 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
468 TII.loadRegFromStackSlot(MBB, MI, Reg, it->getFrameIdx(), RC, TRI);
577 const TargetRegisterClass *RC = &XCore::GRRegsRegClass;
584 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
585 RC->getAlignment(),
588 RS->addScavengingFrameIndex(MFI->CreateStackObject(RC->getSize(),
589 RC->getAlignment(),
|
| /frameworks/av/media/libstagefright/rtsp/ |
| ARTPConnection.cpp | 599 size_t RC = data[0] & 0x1f;
601 if (size < (7 + RC * 6) * 4) {
|
| /external/libogg/win32/ |
| Makefile | 98 RC = @RC@
|
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 381 const TargetRegisterClass *RC = RegClassForVT[VT.SimpleTy];
382 assert(RC && "This value type is not natively supported!");
383 return RC;
394 const TargetRegisterClass *RC = RepRegClassForVT[VT.SimpleTy];
395 return RC;
[all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ScheduleDAGFast.cpp | 581 const TargetRegisterClass *RC =
583 const TargetRegisterClass *DestRC = TRI->getCrossCopyRegClass(RC);
585 // If cross copy register class is the same as RC, then it must be
587 // If cross copy register class is not the same as RC, then it's
593 if (DestRC != RC) {
602 InsertCopiesAndMoveSuccs(LRDef, Reg, DestRC, RC, Copies);
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64FrameLowering.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMBaseRegisterInfo.cpp | 151 const TargetRegisterClass *RC = &ARM::GPRPairRegClass;
152 for(TargetRegisterClass::iterator I = RC->begin(), E = RC->end(); I!=E; ++I)
160 ARMBaseRegisterInfo::getLargestLegalSuperClass(const TargetRegisterClass *RC,
162 const TargetRegisterClass *Super = RC;
163 TargetRegisterClass::sc_iterator I = RC->getSuperClasses();
177 return RC;
187 ARMBaseRegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {
188 if (RC == &ARM::CCRRegClass)
190 return RC;
[all...] |
