| /external/llvm/utils/TableGen/ |
| PseudoLoweringEmitter.cpp | 28 enum MapKind { Operand, Imm, Reg };
33 Record *Reg; // Physical register.
83 OperandMap[BaseIdx + i].Kind = OpData::Reg;
84 OperandMap[BaseIdx + i].Data.Reg = DI->getDef();
238 case OpData::Reg: {
239 Record *Reg = Expansion.OperandMap[MIOpNo + i].Data.Reg;
242 if (Reg->getName() == "zero_reg")
245 o << Reg->getValueAsString("Namespace") << "::"
246 << Reg->getName()
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| FunctionLoweringInfo.h | 179 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg) {
180 if (!LiveOutRegInfo.inBounds(Reg))
183 const LiveOutInfo *LOI = &LiveOutRegInfo[Reg];
195 const LiveOutInfo *GetLiveOutRegInfo(unsigned Reg, unsigned BitWidth);
198 void AddLiveOutRegInfo(unsigned Reg, unsigned NumSignBits,
204 LiveOutRegInfo.grow(Reg);
205 LiveOutInfo &LOI = LiveOutRegInfo[Reg];
223 unsigned Reg = It->second;
224 if (Reg == 0)
227 LiveOutRegInfo.grow(Reg);
[all...] |
| MachineTraceMetrics.h | 121 unsigned Reg;
127 LiveInReg(unsigned Reg, unsigned Height = 0) : Reg(Reg), Height(Height) {}
|
| ScheduleDAGInstrs.h | 60 unsigned Reg;
62 PhysRegSUOper(SUnit *su, int op, unsigned R): SU(su), OpIdx(op), Reg(R) {}
64 unsigned getSparseSetIndex() const { return Reg; }
|
| StackMaps.h | 143 unsigned Reg;
145 Location() : Type(Unprocessed), Size(0), Reg(0), Offset(0) {}
146 Location(LocationType Type, unsigned Size, unsigned Reg, int64_t Offset)
147 : Type(Type), Size(Size), Reg(Reg), Offset(Offset) {}
151 unsigned short Reg;
155 LiveOutReg() : Reg(0), DwarfRegNum(0), Size(0) {}
156 LiveOutReg(unsigned short Reg, unsigned short DwarfRegNum,
158 : Reg(Reg), DwarfRegNum(DwarfRegNum), Size(Size) {
[all...] |
| /external/llvm/include/llvm/Support/ |
| ARMWinEH.h | 40 /// | Stack Adjust |C|L|R| Reg |H|Ret| Function Length |Flg|
61 /// Reg : 3-bit field indicating the index of the last saved non-volatile
63 /// saved (r4-rN, where N is 4 + Reg). If the R bit is set to 1, then
65 /// 8 + Reg). The special case of the R bit being set to 1 and Reg equal
69 /// special case of the R-flag being set and Reg being set to 7 indicates
90 /// + r11 must NOT be included in the set of registers described by Reg
148 uint8_t Reg() const {
172 assert(((~UnwindData & 0x00200000) || (Reg() < 7) || R()) &&
173 "r11 must not be included in Reg; C implies r11")
[all...] |
| /external/llvm/lib/CodeGen/ |
| CriticalAntiDepBreaker.cpp | 62 unsigned Reg = *AI;
63 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
64 KillIndices[Reg] = BBSize;
65 DefIndices[Reg] = ~0u;
77 unsigned Reg = *AI;
78 Classes[Reg] = reinterpret_cast<TargetRegisterClass *>(-1);
79 KillIndices[Reg] = BBSize;
80 DefIndices[Reg] = ~0u;
103 for (unsigned Reg = 0; Reg != TRI->getNumRegs(); ++Reg)
[all...] |
| LiveRangeCalc.cpp | 56 // Step 1: Create minimal live segments for every definition of Reg.
57 // Visit all def operands. If the same instruction has multiple defs of Reg,
60 unsigned Reg = LI.reg;
61 for (const MachineOperand &MO : MRI->reg_nodbg_operands(Reg)) {
68 : MRI->getMaxLaneMaskForVReg(Reg);
73 LaneBitmask ClassMask = MRI->getMaxLaneMaskForVReg(Reg);
120 extendToUses(S, Reg, S.LaneMask);
126 extendToUses(LI, Reg, ~0u);
131 void LiveRangeCalc::createDeadDefs(LiveRange &LR, unsigned Reg) {
[all...] |
| MachineInstrBundle.cpp | 145 unsigned Reg = MO.getReg();
146 if (!Reg)
148 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
149 if (LocalDefSet.count(Reg)) {
153 KilledDefSet.insert(Reg);
155 if (ExternUseSet.insert(Reg).second) {
156 ExternUses.push_back(Reg);
158 UndefUseSet.insert(Reg);
162 KilledUseSet.insert(Reg);
168 unsigned Reg = MO.getReg()
[all...] |
| MachineRegisterInfo.cpp | 40 MachineRegisterInfo::setRegClass(unsigned Reg, const TargetRegisterClass *RC) {
42 VRegInfo[Reg].first = RC;
46 MachineRegisterInfo::constrainRegClass(unsigned Reg,
49 const TargetRegisterClass *OldRC = getRegClass(Reg);
58 setRegClass(Reg, NewRC);
63 MachineRegisterInfo::recomputeRegClass(unsigned Reg) {
65 const TargetRegisterClass *OldRC = getRegClass(Reg);
74 for (MachineOperand &MO : reg_nodbg_operands(Reg)) {
83 setRegClass(Reg, NewRC);
97 unsigned Reg = TargetRegisterInfo::index2VirtReg(getNumVirtRegs())
[all...] |
| MachineSink.cpp | 128 bool AllUsesDominatedByBlock(unsigned Reg, MachineBasicBlock *MBB,
133 bool isProfitableToSinkTo(unsigned Reg, MachineInstr *MI,
195 MachineSinking::AllUsesDominatedByBlock(unsigned Reg,
200 assert(TargetRegisterInfo::isVirtualRegister(Reg) &&
204 if (MRI->use_nodbg_empty(Reg))
223 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
236 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) {
376 unsigned Reg = MO.getReg();
377 if (Reg == 0)
382 if (TargetRegisterInfo::isPhysicalRegister(Reg))
[all...] |
| StackMaps.cpp | 78 static unsigned getDwarfRegNum(unsigned Reg, const TargetRegisterInfo *TRI) {
79 int RegNum = TRI->getDwarfRegNum(Reg, false);
80 for (MCSuperRegIterator SR(Reg, TRI); SR.isValid() && RegNum < 0; ++SR)
102 unsigned Reg = (++MOI)->getReg();
105 getDwarfRegNum(Reg, TRI), Imm);
111 unsigned Reg = (++MOI)->getReg();
114 getDwarfRegNum(Reg, TRI), Imm);
180 OS << TRI->getName(Loc.Reg);
182 OS << Loc.Reg;
187 OS << TRI->getName(Loc.Reg);
[all...] |
| VirtRegMap.cpp | 123 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
124 if (Virt2PhysMap[Reg] != (unsigned)VirtRegMap::NO_PHYS_REG) {
125 OS << '[' << PrintReg(Reg, TRI) << " -> "
126 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
132 unsigned Reg = TargetRegisterInfo::index2VirtReg(i);
133 if (Virt2StackSlotMap[Reg] != VirtRegMap::NO_STACK_SLOT) {
134 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"
[all...] |
| /external/llvm/lib/CodeGen/MIRParser/ |
| MIRParser.cpp | 355 unsigned Reg = RegInfo.createVirtualRegister(RC);
356 if (!PFS.VirtualRegisterSlots.insert(std::make_pair(VReg.ID.Value, Reg))
367 RegInfo.setSimpleHint(Reg, PreferredReg);
373 unsigned Reg = 0;
374 if (parseNamedRegisterReference(Reg, SM, MF, LiveIn.Register.Value, PFS,
383 RegInfo.addLiveIn(Reg, VReg);
391 unsigned Reg = 0;
392 if (parseNamedRegisterReference(Reg, SM, MF, RegSource.Value, PFS, IRSlots,
395 CalleeSavedRegisterMask[Reg] = true;
527 unsigned Reg = 0
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 191 unsigned Reg = MO.getReg();
192 assert(TargetRegisterInfo::isPhysicalRegister(Reg));
194 O << AArch64InstPrinter::getRegisterName(Reg);
218 unsigned Reg = MO.getReg();
223 Reg = getWRegFromXReg(Reg);
226 Reg = getXRegFromWReg(Reg);
230 O << AArch64InstPrinter::getRegisterName(Reg);
243 unsigned Reg = MO.getReg()
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstrInfo.cpp | 169 unsigned Reg, bool UnfoldLoad,
281 unsigned Reg = LI->first;
282 if (TargetRegisterInfo::isVirtualRegister(Reg) ||
283 !IndirectRC->contains(Reg))
290 if (IndirectRC->getRegister(RegIndex) == Reg)
|
| R600OptimizeVectorRegisters.cpp | 50 isImplicitlyDef(MachineRegisterInfo &MRI, unsigned Reg) {
51 for (MachineRegisterInfo::def_instr_iterator It = MRI.def_instr_begin(Reg),
55 if (MRI.isReserved(Reg)) {
58 llvm_unreachable("Reg without a def");
90 bool areAllUsesSwizzeable(unsigned Reg) const;
181 unsigned Reg = RSI->Instr->getOperand(0).getReg();
213 Pos = BuildMI(MBB, Pos, DL, TII->get(AMDGPU::COPY), Reg)
218 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
265 bool R600VectorRegMerger::areAllUsesSwizzeable(unsigned Reg) const {
266 for (MachineRegisterInfo::use_instr_iterator It = MRI->use_instr_begin(Reg),
[all...] |
| SILowerControlFlow.cpp | 92 void computeIndirectRegAndOffset(unsigned VecReg, unsigned &Reg, int &Offset);
186 unsigned Reg = MI.getOperand(0).getReg();
189 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_AND_SAVEEXEC_B64), Reg)
192 BuildMI(MBB, &MI, DL, TII->get(AMDGPU::S_XOR_B64), Reg)
194 .addReg(Reg);
282 unsigned Reg = MI.getOperand(0).getReg();
287 .addReg(Reg);
401 /// \param[out] @Reg The base register to use in the indirect addressing instruction.
407 unsigned &Reg,
423 Reg = RC->getRegister(RegIdx)
[all...] |
| SIRegisterInfo.cpp | 28 void SIRegisterInfo::reserveRegisterTuples(BitVector &Reserved, unsigned Reg) const {
29 MCRegAliasIterator R(Reg, this, true);
100 unsigned Reg = AMDGPU::SGPR_32RegClass.getRegister(i);
101 reserveRegisterTuples(Reserved, Reg);
394 unsigned SIRegisterInfo::getHWRegIndex(unsigned Reg) const {
395 return getEncodingValue(Reg) & 0xff;
400 const TargetRegisterClass *SIRegisterInfo::getPhysRegClass(unsigned Reg) const {
401 assert(!TargetRegisterInfo::isVirtualRegister(Reg));
418 if (BaseClass->contains(Reg)) {
504 unsigned SIRegisterInfo::getPhysRegSubReg(unsigned Reg,
[all...] |
| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 66 bool hasRAWHazard(unsigned Reg, MachineInstr *MI) const;
90 unsigned Reg = MI->getOperand(1).getReg();
91 if (TargetRegisterInfo::isPhysicalRegister(Reg))
95 MachineInstr *DefMI = MRI->getVRegDef(Reg);
100 Reg = DefMI->getOperand(1).getReg();
101 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
102 DefMI = MRI->getVRegDef(Reg);
106 Reg = DefMI->getOperand(2).getReg();
107 if (TargetRegisterInfo::isVirtualRegister(Reg)) {
108 DefMI = MRI->getVRegDef(Reg);
[all...] |
| Thumb1FrameLowering.cpp | 147 unsigned Reg = CSI[i].getReg();
149 switch (Reg) {
164 if (Reg == FramePtr)
208 unsigned Reg = I->getReg();
210 switch (Reg) {
229 nullptr, MRI->getDwarfRegNum(Reg, true), MFI->getObjectOffset(FI)));
498 // form the GPR reg class for thumb1.
587 unsigned Reg = CSI[i-1].getReg();
593 if (Reg == ARM::LR) {
596 MF.getRegInfo().isLiveIn(Reg))
[all...] |
| Thumb2ITBlockPass.cpp | 67 unsigned Reg = MO.getReg();
68 if (!Reg || Reg == ARM::ITSTATE || Reg == ARM::SP)
71 LocalUses.push_back(Reg);
73 LocalDefs.push_back(Reg);
77 unsigned Reg = LocalUses[i];
78 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
84 unsigned Reg = LocalDefs[i];
85 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true)
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| BitTracker.h | 46 bool has(unsigned Reg) const;
47 const RegisterCell &lookup(unsigned Reg) const;
57 void visitUsesOf(unsigned Reg);
77 // Abstraction of a reference to bit at position Pos from a register Reg.
79 BitRef(unsigned R = 0, uint16_t P = 0) : Reg(R), Pos(P) {}
81 // If Reg is 0, disregard Pos.
82 return Reg == BR.Reg && (Reg == 0 || Pos == BR.Pos);
84 unsigned Reg;
[all...] |
| HexagonAsmPrinter.cpp | 73 inline static unsigned getHexagonRegisterPair(unsigned Reg,
75 assert(Hexagon::IntRegsRegClass.contains(Reg));
76 MCSuperRegIterator SR(Reg, RI, false);
278 MCOperand &Reg = MappedInst.getOperand(0);
280 TmpInst.addOperand(Reg);
297 MCOperand &Reg = MappedInst.getOperand(0);
299 TmpInst.addOperand(Reg);
322 unsigned Reg = RI->getEncodingValue(Rt.getReg());
323 if (Reg & 1)
333 unsigned Reg = RI->getEncodingValue(Rt.getReg())
[all...] |
| HexagonNewValueJump.cpp | 156 unsigned Reg = II->getOperand(i).getReg();
161 if (localBegin->modifiesRegister(Reg, TRI) ||
162 localBegin->readsRegister(Reg, TRI))
287 static unsigned getNewValueJumpOpcode(MachineInstr *MI, int reg,
306 if (reg >= 0)
324 if (reg >= 0)
423 unsigned predReg = 0; // predicate reg of the jump.
524 // We need cmpReg1 and cmpOp2(imm or reg) while building
|
