| /external/llvm/lib/CodeGen/ |
| MachineCombiner.cpp | 445 const TargetSubtargetInfo &STI = MF.getSubtarget();
446 TII = STI.getInstrInfo();
447 TRI = STI.getRegisterInfo();
448 SchedModel = STI.getSchedModel();
449 TSchedModel.init(SchedModel, &STI, TII);
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| EarlyIfConversion.cpp | 789 const TargetSubtargetInfo &STI = MF.getSubtarget();
790 if (!STI.enableEarlyIfConversion())
793 TII = STI.getInstrInfo();
794 TRI = STI.getRegisterInfo();
795 SchedModel = STI.getSchedModel();
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 46 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
47 TRI = STI.getRegisterInfo();
49 TII = STI.getInstrInfo();
50 ResourcesModel.reset(TII->CreateTargetScheduleState(STI));
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| ScheduleDAGRRList.cpp | 169 const TargetSubtargetInfo &STI = mf.getSubtarget();
173 HazardRec = STI.getInstrInfo()->CreateTargetHazardRecognizer(&STI, this);
[all...] |
| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 127 const AMDGPUSubtarget &STI = MF.getSubtarget<AMDGPUSubtarget>();
129 unsigned SGPRLimit = getNumSGPRsAllowed(STI.getGeneration(),
130 STI.getMaxWavesPerCU());
131 unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
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| /external/llvm/lib/Target/ARM/ |
| MLxExpansionPass.cpp | 384 const ARMSubtarget *STI = &Fn.getSubtarget<ARMSubtarget>();
386 if (!STI->isCortexA9())
388 isLikeA9 = STI->isLikeA9() || STI->isSwift();
389 isSwift = STI->isSwift();
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| Thumb2ITBlockPass.cpp | 270 const ARMSubtarget &STI =
272 if (!STI.isThumb2())
275 TII = static_cast<const Thumb2InstrInfo *>(STI.getInstrInfo());
276 TRI = STI.getRegisterInfo();
277 restrictIT = STI.restrictIT();
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| A15SDOptimizer.cpp | 684 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
687 if (!(STI.isCortexA15() && STI.hasNEON()))
689 TII = STI.getInstrInfo();
690 TRI = STI.getRegisterInfo();
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| ARMBaseRegisterInfo.cpp | 51 static unsigned getFramePointerReg(const ARMSubtarget &STI) {
52 if (STI.isTargetMachO()) {
53 if (STI.isTargetDarwin() || STI.isThumb1Only())
57 } else if (STI.isTargetWindows())
60 return STI.isThumb() ? ARM::R7 : ARM::R11;
65 const ARMSubtarget &STI = MF->getSubtarget<ARMSubtarget>();
67 STI.isTargetDarwin() ? CSR_iOS_SaveList : CSR_AAPCS_SaveList;
75 if (STI.isMClass()) {
96 const ARMSubtarget &STI = MF.getSubtarget<ARMSubtarget>()
[all...] |
| Thumb2SizeReduction.cpp | 142 const ARMSubtarget *STI;
257 if (MinimizeSize || !STI->avoidCPSRPartialUpdate())
653 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
771 if (!OptimizeSize && Entry.AvoidMovs && STI->avoidMOVsShifterOperand())
[all...] |
| ARMExpandPseudoInsts.cpp | 48 const ARMSubtarget *STI;
[all...] |
| ARMLoadStoreOptimizer.cpp | 81 const ARMSubtarget *STI;
685 !STI->hasV6Ops()) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 212 const TargetSubtargetInfo &STI = DAG->MF.getSubtarget();
213 const TargetInstrInfo *TII = STI.getInstrInfo();
221 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
222 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
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| /external/llvm/lib/Target/Mips/ |
| MipsLongBranch.cpp | 451 const MipsSubtarget &STI =
454 static_cast<const MipsInstrInfo *>(STI.getInstrInfo());
456 !IsPIC ? 2 : (ABI.IsN64() ? 10 : (!STI.isTargetNaCl() ? 9 : 10));
458 if (STI.inMips16Mode() || !STI.enableLongBranchPass())
483 int ShVal = STI.inMicroMipsMode() ? 2 : 4;
486 if (STI.isTargetNaCl()) {
|
| MipsSEInstrInfo.cpp | 27 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
28 : MipsInstrInfo(STI, STI.getRelocationModel() == Reloc::PIC_ ? Mips::B
453 const MipsSubtarget &STI = Subtarget;
455 unsigned Size = STI.isABI_N64() ? 64 : 32;
456 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
457 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
458 const TargetRegisterClass *RC = STI.isABI_N64() ?
711 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
712 return new MipsSEInstrInfo(STI);
[all...] |
| MipsDelaySlotFiller.cpp | 571 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
572 bool InMicroMipsMode = STI.inMicroMipsMode();
573 const MipsInstrInfo *TII = STI.getInstrInfo();
683 const MipsSubtarget &STI = MBB.getParent()->getSubtarget<MipsSubtarget>();
684 if (STI.isTargetNaCl()) {
692 CurrI->modifiesRegister(Mips::SP, STI.getRegisterInfo()))
696 bool InMicroMipsMode = STI.inMicroMipsMode();
697 const MipsInstrInfo *TII = STI.getInstrInfo();
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 328 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
329 if (!STI.hasVSX())
334 TII = STI.getInstrInfo();
|
| PPCVSXSwapRemoval.cpp | 197 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
198 if (!STI.hasVSX())
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 119 SystemZSubtarget &STI;
137 explicit SystemZInstrInfo(SystemZSubtarget &STI);
|
| /external/llvm/lib/Target/X86/ |
| X86CallFrameOptimization.cpp | 107 const X86Subtarget *STI;
131 if (STI->is64Bit())
137 if (STI->isTargetDarwin() &&
222 STI = &MF.getSubtarget<X86Subtarget>();
223 TII = STI->getInstrInfo();
224 TFL = STI->getFrameLowering();
319 STI->getRegisterInfo());
481 bool SlowPUSHrmm = STI->isAtom() || STI->isSLM();
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
|
| R600MCCodeEmitter.cpp | 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.h | 79 MCSubtargetInfo const &STI;
197 explicit HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst& mcb, MCInst &mcbdx,
|
| HexagonShuffler.h | 142 MCSubtargetInfo const &STI;
160 explicit HexagonShuffler(MCInstrInfo const &MCII, MCSubtargetInfo const &STI);
|
| /external/llvm/include/llvm/MC/ |
| MCAssembler.h | 268 /// STI - The MCSubtargetInfo in effect when the instruction was encoded.
269 const MCSubtargetInfo &STI;
272 MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,
275 Inst(Inst), STI(STI) {}
280 const MCSubtargetInfo &getSubtargetInfo() { return STI; }
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