| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-aarch64/ |
| ifunc-6.s | 20 adrp x0, :got:foo
|
| ifunc-7.s | 20 adrp x0, :got:foo
|
| ifunc-9.s | 18 adrp x0, .LANCHOR0
|
| tls-relax-gd-ie.d | 5 +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
|
| tls-relax-gdesc-ie-2.s | 8 adrp x0, :tlsdesc:var
|
| tls-relax-gdesc-ie.d | 5 +10000: 90000080 adrp x0, 20000 <_GLOBAL_OFFSET_TABLE_>
|
| tls-relax-gdesc-le-2.s | 7 adrp x0, :tlsdesc:var
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| reloc-insn.s | 71 adrp x0,llit
72 adrp x1,ldata
73 adrp x2,ldata+4088
74 adrp x3,xlit
75 adrp x4,xdata+16
76 adrp x5,xdata+4088
79 adrp x0,:pg_hi21:llit
80 adrp x1,:pg_hi21:ldata
81 adrp x2,:pg_hi21:ldata+4088
82 adrp x3,:pg_hi21:xli
[all...] |
| tls.d | 8 0: 90000000 adrp x0, 0 <var>
16 10: 90000000 adrp x0, 0 <var>
22 1c: 90000000 adrp x0, 0 <var>
|
| tls.s | 25 adrp x0, :tlsdesc:var
35 adrp x0, :tlsgd:var
42 adrp x0, :gottprel:var
|
| reloc-insn.d | 56 8c: 90000000 adrp x0, 0 <func>
58 90: 90000001 adrp x1, 0 <func>
60 94: 90000002 adrp x2, 0 <func>
62 98: 90000003 adrp x3, 0 <xlit>
64 9c: 90000004 adrp x4, 0 <xdata>
66 a0: 90000005 adrp x5, 0 <xdata>
68 a4: 90000000 adrp x0, 0 <func>
70 a8: 90000001 adrp x1, 0 <func>
72 ac: 90000002 adrp x2, 0 <func>
74 b0: 90000003 adrp x3, 0 <xlit
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-fast-isel-intrinsic.ll | 8 ; ARM64: adrp x8, _message@PAGE
22 ; ARM64: adrp x8, _temp@GOTPAGE
24 ; ARM64: adrp x8, _message@PAGE
36 ; ARM64: adrp x8, _temp@GOTPAGE
38 ; ARM64: adrp x8, _message@PAGE
50 ; ARM64: adrp x8, _temp@GOTPAGE
52 ; ARM64: adrp x9, _message@PAGE
67 ; ARM64: adrp x8, _temp@GOTPAGE
69 ; ARM64: adrp x9, _message@PAGE
84 ; ARM64: adrp x8, _temp@GOTPAG
[all...] |
| global-merge-2.ll | 11 ;CHECK-APPLE-IOS-NOT: adrp
12 ;CHECK-APPLE-IOS: adrp x8, l__MergedGlobals@PAGE
14 ;CHECK-APPLE-IOS-NOT: adrp
22 ;CHECK-APPLE-IOS: adrp x8, l__MergedGlobals@PAGE
24 ;CHECK-APPLE-IOS-NOT: adrp
|
| global-alignment.ll | 15 ; CHECK: adrp [[HIBITS:x[0-9]+]], var32
26 ; However, var64 *is* properly aligned and emitting an adrp/add/ldr would be
29 ; CHECK: adrp x[[HIBITS:[0-9]+]], var64
43 ; CHECK: adrp x[[HIBITS:[0-9]+]], var32_align64
56 ; CHECK: adrp x[[HIBITS:[0-9]+]], alias
72 ; CHECK: adrp [[HIBITS:x[0-9]+]], yet_another_var
81 ; CHECK: adrp [[HIBITS:x[0-9]+]], test_yet_another_var
|
| arm64-extern-weak.ll | 8 ; The usual ADRP/ADD pair can't be used for a weak reference because it must
13 ; CHECK: adrp x[[VAR:[0-9]+]], :got:var
18 ; CHECK-STATIC: adrp x[[VAR:[0-9]+]], .LCPI0_0
34 ; CHECK: adrp x[[ARR_VAR_HI:[0-9]+]], :got:arr_var
56 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
59 ; CHECK-STATIC: adrp [[BASE:x[0-9]+]], defined_weak_var
|
| extern-weak.ll | 8 ; The usual ADRP/ADD pair can't be used for a weak reference because it must
14 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:var
19 ; CHECK-STATIC: adrp x[[VAR:[0-9]+]], .LCPI0_0
37 ; CHECK: adrp x[[ADDRHI:[0-9]+]], :got:arr_var
61 ; CHECK: adrp [[BASE:x[0-9]+]], defined_weak_var
64 ; CHECK-STATIC: adrp [[BASE:x[0-9]+]], defined_weak_var
|
| global-merge-ignore-single-use-minsize.ll | 14 ; CHECK-NEXT: adrp x8, [[SET:l__MergedGlobals]]@PAGE
28 ; CHECK-NEXT: adrp x8, _m2@PAGE
29 ; CHECK-NEXT: adrp x9, _n2@PAGE
47 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
60 ; CHECK-NEXT: adrp x8, [[SET]]@PAGE
62 ; CHECK-NEXT: adrp x9, _n4@PAGE
|
| arm64-elf-constpool.ll | 11 ; CHECK: adrp {{x[0-9]+}}, .LCPI0_0
|
| arm64-global-address.ll | 8 ; CHECK: adrp x[[REG:[0-9]+]], _G@GOTPAGE
|
| breg.ll | 9 ; CHECK: adrp {{x[0-9]+}}, stored_label
|
| funcptr_cast.ll | 5 ; CHECK: adrp {{x[0-9]+}}, foo
|
| /art/compiler/linker/arm64/ |
| relative_patcher_arm64.cc | 70 // Count the number of ADRP insns as the upper bound on the number of thunks needed
84 // Now that we have the actual offset where the code will be placed, locate the ADRP insns
176 // Check it's an ADRP with imm == 0 (unset).
185 uint32_t adrp = PatchAdrp(insn, adrp_disp); local
200 SetInsn(¤t_method_thunks_, thunks_code_offset, adrp);
208 // Write the new ADRP (or B to the erratum 843419 thunk).
221 uint32_t adrp = GetInsn(code, pc_insn_offset); local
222 if ((adrp & 0x9f000000u) != 0x90000000u) {
224 CHECK_EQ(adrp & 0xfc000000u, 0x14000000u); // B <thunk>
233 adrp = GetInsn(¤t_method_thunks_, idx * kAdrpThunkSize)
283 uint32_t adrp = GetInsn(code, literal_offset); local
[all...] |
| /external/llvm/test/ExecutionEngine/RuntimeDyld/AArch64/ |
| MachO_ARM64_relocations.s | 26 # Test ARM64_RELOC_PAGE21 and ARM64_RELOC_PAGEOFF12 relocation. adrp encodes
27 # the PC-relative page (4 KiB) difference between the adrp instruction and the
36 adrp x0, _ptr@PAGE
42 # relocation. adrp encodes the PC-relative page (4 KiB) difference between the
43 # adrp instruction and the GOT entry for ptr. ldr encodes the offset of the GOT
53 adrp x0, _ptr@GOTPAGE
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CollectLOH.cpp | 20 // L1: adrp xA, sym@PAGE
29 // L1: adrp xA, sym@PAGE
40 // respectively ADRP, ADD (immediate), and LD.
46 // - The ADRP in L1 and the ADD in L2 must reference the same symbol using
50 // * So called non-ADRP-related:
52 // L1: adrp xA, sym@PAGE
56 // L1: adrp xA, sym@GOTPAGE
60 // L1: adrp xA, sym@PAGE
63 // L1: adrp xA, sym@PAGE
67 // L1: adrp xA, sym@GOTPAG
[all...] |
| /external/llvm/include/llvm/MC/ |
| MCLinkerOptimizationHint.h | 34 MCLOH_AdrpAdrp = 0x1u, ///< Adrp xY, _v1@PAGE -> Adrp xY, _v2@PAGE.
35 MCLOH_AdrpLdr = 0x2u, ///< Adrp _v@PAGE -> Ldr _v@PAGEOFF.
36 MCLOH_AdrpAddLdr = 0x3u, ///< Adrp _v@PAGE -> Add _v@PAGEOFF -> Ldr.
37 MCLOH_AdrpLdrGotLdr = 0x4u, ///< Adrp _v@GOTPAGE -> Ldr _v@GOTPAGEOFF -> Ldr.
38 MCLOH_AdrpAddStr = 0x5u, ///< Adrp _v@PAGE -> Add _v@PAGEOFF -> Str.
39 MCLOH_AdrpLdrGotStr = 0x6u, ///< Adrp _v@GOTPAGE -> Ldr _v@GOTPAGEOFF -> Str.
40 MCLOH_AdrpAdd = 0x7u, ///< Adrp _v@PAGE -> Add _v@PAGEOFF.
41 MCLOH_AdrpLdrGot = 0x8u ///< Adrp _v@GOTPAGE -> Ldr _v@GOTPAGEOFF.
|
