/external/llvm/lib/CodeGen/ |
ProcessImplicitDefs.cpp | 31 MachineRegisterInfo *MRI; 84 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 144 MRI = &MF.getRegInfo(); 145 assert(MRI->isSSA() && "ProcessImplicitDefs only works on SSA form.");
|
VirtRegMap.cpp | 57 MRI = &mf.getRegInfo(); 85 unsigned Hint = MRI->getSimpleHint(VirtReg); 94 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(VirtReg); 122 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; 131 for (unsigned i = 0, e = MRI->getNumVirtRegs(); i != e; ++i) { 135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n"; 162 MachineRegisterInfo *MRI; 213 MRI = &MF->getRegInfo(); 237 MRI->clearVirtRegs() [all...] |
PeepholeOptimizer.cpp | 126 MachineRegisterInfo *MRI; 310 const MachineRegisterInfo &MRI; 351 const MachineRegisterInfo &MRI, 355 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) { 357 Def = MRI.getVRegDef(Reg); 358 DefIdx = MRI.def_begin(Reg).getOperandNo(); 370 const MachineRegisterInfo &MRI, 374 UseAdvancedTracking(UseAdvancedTracking), MRI(MRI), TII(TII) [all...] |
DeadMachineInstructionElim.cpp | 35 const MachineRegisterInfo *MRI; 78 if (LivePhysRegs.test(Reg) || MRI->isReserved(Reg)) 81 if (!MRI->use_nodbg_empty(Reg)) 97 MRI = &MF.getRegInfo(); 106 LivePhysRegs = MRI->getReservedRegs();
|
MachineSink.cpp | 59 MachineRegisterInfo *MRI; // Machine register information 166 !MRI->hasOneNonDBGUse(SrcReg)) 169 const TargetRegisterClass *SRC = MRI->getRegClass(SrcReg); 170 const TargetRegisterClass *DRC = MRI->getRegClass(DstReg); 174 MachineInstr *DefMI = MRI->getVRegDef(SrcReg); 179 MRI->replaceRegWith(DstReg, SrcReg); 184 MRI->clearKillFlags(SrcReg); 204 if (MRI->use_nodbg_empty(Reg)) 223 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) { 236 for (MachineOperand &MO : MRI->use_nodbg_operands(Reg)) [all...] |
MachineSSAUpdater.cpp | 43 MRI = &MF.getRegInfo(); 59 VRC = MRI->getRegClass(VR); 117 MachineRegisterInfo *MRI, 119 unsigned NewVR = MRI->createVirtualRegister(RC); 153 VRC, MRI, TII); 189 Loc, VRC, MRI, TII); 290 Updater->VRC, Updater->MRI, 301 Updater->VRC, Updater->MRI, 324 return InstrIsPHI(Updater->MRI->getVRegDef(Val));
|
TargetInstrInfo.cpp | 387 const MachineRegisterInfo *MRI) const { 419 const MachineRegisterInfo &MRI = MI->getParent()->getParent()->getRegInfo(); 420 const TargetRegisterClass *RC = MRI.getRegClass(FoldReg); 425 if (RC->hasSubClassEq(MRI.getRegClass(LiveReg))) 567 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 574 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); 576 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); 585 const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo(); 586 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); 587 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()) [all...] |
TargetFrameLoweringImpl.cpp | 78 const MachineRegisterInfo &MRI = MF.getRegInfo(); 81 if (CallsUnwindInit || MRI.isPhysRegModified(Reg))
|
/external/llvm/lib/Target/AMDGPU/InstPrinter/ |
AMDGPUInstPrinter.cpp | 131 const MCRegisterInfo &MRI) { 173 if (MRI.getRegClass(AMDGPU::VGPR_32RegClassID).contains(reg)) { 176 } else if (MRI.getRegClass(AMDGPU::SGPR_32RegClassID).contains(reg)) { 179 } else if (MRI.getRegClass(AMDGPU::VReg_64RegClassID).contains(reg)) { 182 } else if (MRI.getRegClass(AMDGPU::SReg_64RegClassID).contains(reg)) { 185 } else if (MRI.getRegClass(AMDGPU::VReg_128RegClassID).contains(reg)) { 188 } else if (MRI.getRegClass(AMDGPU::SReg_128RegClassID).contains(reg)) { 191 } else if (MRI.getRegClass(AMDGPU::VReg_96RegClassID).contains(reg)) { 194 } else if (MRI.getRegClass(AMDGPU::VReg_256RegClassID).contains(reg)) { 197 } else if (MRI.getRegClass(AMDGPU::SReg_256RegClassID).contains(reg)) [all...] |
/external/llvm/lib/Target/Mips/MCTargetDesc/ |
MipsMCTargetDesc.cpp | 74 static MCAsmInfo *createMipsMCAsmInfo(const MCRegisterInfo &MRI, 78 unsigned SP = MRI.getDwarfRegNum(Mips::SP, true); 101 const MCRegisterInfo &MRI) { 102 return new MipsInstPrinter(MAI, MII, MRI);
|
/external/llvm/lib/Target/WebAssembly/ |
WebAssemblyStoreResults.cpp | 72 const MachineRegisterInfo &MRI = MF.getRegInfo(); 76 assert(MRI.isSSA() && "StoreResults depends on SSA form"); 95 for (auto I = MRI.use_begin(FromReg), E = MRI.use_end(); I != E;) {
|
WebAssemblyFrameLowering.cpp | 73 auto &MRI = MF.getRegInfo(); 74 unsigned SPReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); 89 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass); 149 auto &MRI = MF.getRegInfo(); 150 unsigned OffsetReg = MRI.createVirtualRegister(&WebAssembly::I32RegClass);
|
/external/svox/pico/lib/ |
picokdbg.h | 26 *- 0.1, 08.05.2008, MRi - initial version
|
/toolchain/binutils/binutils-2.25/gas/testsuite/gas/mri/ |
moveml.d | 2 #name: MRI moveml
|
/external/llvm/lib/Target/AMDGPU/ |
SIInstrInfo.h | 30 MachineRegisterInfo &MRI, 36 MachineRegisterInfo &MRI, 59 unsigned Reg, MachineRegisterInfo &MRI, 146 unsigned Reg, MachineRegisterInfo *MRI) const final; 318 bool usesConstantBus(const MachineRegisterInfo &MRI, 387 bool isLegalVSrcOperand(const MachineRegisterInfo &MRI, 393 bool isLegalRegOperand(const MachineRegisterInfo &MRI, 399 void legalizeOperandsVOP2(MachineRegisterInfo &MRI, MachineInstr *MI) const; 402 void legalizeOperandsVOP3(MachineRegisterInfo &MRI, MachineInstr *MI) const; 414 void moveSMRDToVALU(MachineInstr *MI, MachineRegisterInfo &MRI, [all...] |
/external/llvm/lib/Target/AArch64/ |
AArch64InstrInfo.cpp | 283 static unsigned removeCopies(const MachineRegisterInfo &MRI, unsigned VReg) { 285 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 296 static unsigned canFoldIntoCSel(const MachineRegisterInfo &MRI, unsigned VReg, 298 VReg = removeCopies(MRI, VReg); 302 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); 303 const MachineInstr *DefMI = MRI.getVRegDef(VReg); 326 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); 343 unsigned ZReg = removeCopies(MRI, DefMI->getOperand(1).getReg()); 365 const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo(); 367 RI.getCommonSubClass(MRI.getRegClass(TrueReg), MRI.getRegClass(FalseReg)) [all...] |
/external/llvm/lib/Target/X86/ |
X86VZeroUpper.cpp | 108 static bool checkFnHasLiveInYmm(MachineRegisterInfo &MRI) { 109 for (MachineRegisterInfo::livein_iterator I = MRI.livein_begin(), 110 E = MRI.livein_end(); I != E; ++I) 254 MachineRegisterInfo &MRI = MF.getRegInfo(); 257 bool FnHasLiveInYmm = checkFnHasLiveInYmm(MRI); 267 if (!MRI.reg_nodbg_empty(*i)) {
|
/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.cpp | 230 const MachineRegisterInfo &MRI = MF.getRegInfo(); 231 std::pair<unsigned, unsigned> Hint = MRI.getRegAllocationHint(VirtReg); 272 if (!Paired || MRI.isReserved(Paired)) 281 MachineRegisterInfo *MRI = &MF.getRegInfo(); 282 std::pair<unsigned, unsigned> Hint = MRI->getRegAllocationHint(Reg); 291 Hint = MRI->getRegAllocationHint(OtherReg); 294 MRI->setRegAllocationHint(OtherReg, Hint.first, NewReg); 296 MRI->setRegAllocationHint(NewReg, 335 const MachineRegisterInfo *MRI = &MF.getRegInfo(); 348 if (!MRI->canReserveReg(getFramePointerReg(MF.getSubtarget<ARMSubtarget>())) [all...] |
/external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
AMDGPUMCTargetDesc.cpp | 72 const MCRegisterInfo &MRI) { 73 return new AMDGPUInstPrinter(MAI, MII, MRI);
|
/external/llvm/lib/Target/BPF/MCTargetDesc/ |
BPFAsmBackend.cpp | 97 const MCRegisterInfo &MRI, 103 const MCRegisterInfo &MRI,
|
BPFMCTargetDesc.cpp | 73 const MCRegisterInfo &MRI) { 75 return new BPFInstPrinter(MAI, MII, MRI);
|
/external/llvm/lib/Target/MSP430/MCTargetDesc/ |
MSP430MCTargetDesc.cpp | 64 const MCRegisterInfo &MRI) { 66 return new MSP430InstPrinter(MAI, MII, MRI);
|
/external/llvm/lib/Target/Mips/InstPrinter/ |
MipsInstPrinter.h | 81 const MCRegisterInfo &MRI) 82 : MCInstPrinter(MAI, MII, MRI) {}
|
/external/llvm/lib/Target/NVPTX/MCTargetDesc/ |
NVPTXMCTargetDesc.cpp | 68 const MCRegisterInfo &MRI) { 70 return new NVPTXInstPrinter(MAI, MII, MRI);
|
/external/llvm/lib/Target/PowerPC/InstPrinter/ |
PPCInstPrinter.h | 27 const MCRegisterInfo &MRI, bool isDarwin) 28 : MCInstPrinter(MAI, MII, MRI), IsDarwin(isDarwin) {}
|