| /toolchain/binutils/binutils-2.25/ld/ |
| ldlex.l | 83 MRI in an MRI script
117 %s MRI
147 <MRI,EXPRESSION>"$"([0-9A-Fa-f])+ {
153 <MRI,EXPRESSION>([0-9A-Fa-f])+(H|h|X|x|B|b|O|o|D|d) {
178 <SCRIPT,DEFSYMEXP,MRI,BOTH,EXPRESSION>((("$"|0[xX])([0-9A-Fa-f])+)|(([0-9])+))(M|K|m|k)? {
207 <BOTH,SCRIPT,EXPRESSION,MRI>"]" { RTOKEN(']');}
208 <BOTH,SCRIPT,EXPRESSION,MRI>"[" { RTOKEN('[');}
209 <BOTH,SCRIPT,EXPRESSION,MRI>"<<=" { RTOKEN(LSHIFTEQ);}
210 <BOTH,SCRIPT,EXPRESSION,MRI>">>=" { RTOKEN(RSHIFTEQ);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mri/ |
| mri.exp | 18 # Test the m68k MRI compatibility mode.
20 # I originally thought that most of tests applied to any MRI
21 # assembler, but it turns out that different MRI assemblers use
29 # These tests are generic MRI tests: they don't rely on M68K opcodes.
37 gas_test "empty.s" "-M" "" "MRI empty macro"
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| for.s | 1 ; Test MRI structured for pseudo-op.
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| if.s | 1 ; Test MRI structured if pseudo-op.
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| semi.d | 2 #name: MRI semi
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| repeat.d | 2 #name: MRI structured repeat
5 # Test MRI structured repeat pseudo-op.
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| while.d | 2 #name: MRI structured while
5 # Test MRI structure while pseudo-op.
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| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMAsmBackendDarwin.h | 19 const MCRegisterInfo &MRI;
23 const MCRegisterInfo &MRI, MachO::CPUSubTypeARM st)
24 : ARMAsmBackend(T, TT, /* IsLittleEndian */ true), MRI(MRI), Subtype(st) {
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| ARMMCTargetDesc.h | 60 const MCRegisterInfo &MRI,
64 const MCRegisterInfo &MRI,
67 MCAsmBackend *createARMAsmBackend(const Target &T, const MCRegisterInfo &MRI,
71 MCAsmBackend *createARMLEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
74 MCAsmBackend *createARMBEAsmBackend(const Target &T, const MCRegisterInfo &MRI,
78 const MCRegisterInfo &MRI,
82 const MCRegisterInfo &MRI,
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| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-scripts/ |
| scriptm.t | 0 * MRI script
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyRegColoring.cpp | 63 static float computeWeight(const MachineRegisterInfo *MRI,
67 for (MachineOperand &MO : MRI->reg_nodbg_operands(VReg))
86 MachineRegisterInfo *MRI = &MF.getRegInfo();
93 unsigned NumVRegs = MRI->getNumVirtRegs();
103 if (MRI->use_empty(VReg))
108 LI->weight = computeWeight(MRI, MBFI, VReg);
119 [MRI](LiveInterval *LHS, LiveInterval *RHS) {
120 if (MRI->isLiveIn(LHS->reg) != MRI->isLiveIn(RHS->reg))
121 return MRI->isLiveIn(LHS->reg)
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCTargetDesc.h | 39 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI,
46 const MCRegisterInfo &MRI,
49 const MCRegisterInfo &MRI,
52 const MCRegisterInfo &MRI,
55 const MCRegisterInfo &MRI,
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| /external/mesa3d/src/gallium/drivers/radeon/InstPrinter/ |
| AMDGPUInstPrinter.h | 14 const MCRegisterInfo &MRI)
15 : MCInstPrinter(MAI, MII, MRI) {}
|
| /toolchain/binutils/binutils-2.25/ld/po/ |
| POTFILES.in | 30 mri.c
31 mri.h
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| SIAssignInterpRegs.cpp | 38 void AddLiveIn(MachineFunction * MF, MachineRegisterInfo & MRI,
90 MachineRegisterInfo &MRI = MF.getRegInfo();
97 !MRI.use_empty(InterpUse[interp_idx].regs[reg_idx]);
113 unsigned virt_reg = MRI.createVirtualRegister(&AMDGPU::VReg_32RegClass);
114 MRI.replaceRegWith(InterpUse[interp_idx].regs[reg_idx], virt_reg);
115 AddLiveIn(&MF, MRI, new_reg, virt_reg);
123 MachineRegisterInfo & MRI,
127 if (!MRI.isLiveIn(physReg)) {
128 MRI.addLiveIn(physReg, virtReg);
134 MRI.replaceRegWith(virtReg, MRI.getLiveInVirtReg(physReg))
[all...] |
| SIISelLowering.h | 33 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
35 MachineBasicBlock::iterator I, MachineRegisterInfo &MRI) const;
37 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
39 MachineBasicBlock::iterator I, MachineRegisterInfo & MRI) const;
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| /external/llvm/lib/Target/WebAssembly/MCTargetDesc/ |
| WebAssemblyMCCodeEmitter.cpp | 31 const MCRegisterInfo &MRI;
34 WebAssemblyMCCodeEmitter(const MCInstrInfo &, const MCRegisterInfo &mri,
36 : MRI(mri) {}
63 const MCRegisterInfo &MRI,
65 return new WebAssemblyMCCodeEmitter(MCII, MRI, Ctx);
72 return MRI.getEncodingValue(MO.getReg());
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| /external/llvm/lib/Target/AMDGPU/ |
| SIShrinkInstructions.cpp | 76 const MachineRegisterInfo &MRI) {
81 return TRI.hasVGPRs(MRI.getRegClass(MO->getReg()));
88 const MachineRegisterInfo &MRI) {
102 if (!isVGPR(Src2, TRI, MRI) ||
116 if (Src1 && (!isVGPR(Src1, TRI, MRI) || (Src1Mod && Src1Mod->getImm() != 0)))
139 MachineRegisterInfo &MRI, bool TryToCommute = true) {
141 if (!MRI.isSSA())
159 if (Src0.isReg() && !isVGPR(&Src0, TRI, MRI))
163 if (Src0.isReg() && MRI.hasOneUse(Src0.getReg())) {
165 MachineInstr *Def = MRI.getUniqueVRegDef(Reg)
[all...] |
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 32 const MCRegisterInfo &MRI;
36 BPFMCCodeEmitter(const MCRegisterInfo &mri, bool IsLittleEndian)
37 : MRI(mri), IsLittleEndian(IsLittleEndian) {}
64 const MCRegisterInfo &MRI,
66 return new BPFMCCodeEmitter(MRI, true);
70 const MCRegisterInfo &MRI,
72 return new BPFMCCodeEmitter(MRI, false);
80 return MRI.getEncodingValue(MO.getReg());
159 Encoding = MRI.getEncodingValue(Op1.getReg())
[all...] |
| BPFMCTargetDesc.h | 39 const MCRegisterInfo &MRI,
42 const MCRegisterInfo &MRI,
45 MCAsmBackend *createBPFAsmBackend(const Target &T, const MCRegisterInfo &MRI,
47 MCAsmBackend *createBPFbeAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 72 MachineRegisterInfo *MRI;
113 const MachineRegisterInfo *MRI) {
117 return MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::GPR64RegClass);
122 const MachineRegisterInfo *MRI) {
124 return (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR64RegClass) &&
126 (MRI->getRegClass(Reg)->hasSuperClassEq(&AArch64::FPR128RegClass) &&
136 const MachineRegisterInfo *MRI,
153 MRI) &&
154 isGPR64(MI->getOperand(1).getReg(), MI->getOperand(1).getSubReg(), MRI))
157 MRI) &
[all...] |
| /external/llvm/lib/CodeGen/ |
| CalcSpillWeights.cpp | 35 MachineRegisterInfo &MRI = MF.getRegInfo();
37 for (unsigned i = 0, e = MRI.getNumVirtRegs(); i != e; ++i) {
39 if (MRI.reg_nodbg_empty(Reg))
48 const MachineRegisterInfo &mri) {
66 const TargetRegisterClass *rc = mri.getRegClass(reg);
132 MachineRegisterInfo &mri = MF.getRegInfo(); local
146 bool noHint = mri.getRegAllocationHint(li.reg).first != 0;
152 I = mri.reg_instr_begin(li.reg), E = mri.reg_instr_end();
186 unsigned hint = copyHint(mi, li.reg, tri, mri);
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| AMDGPUMCTargetDesc.h | 39 const MCRegisterInfo &MRI,
43 const MCRegisterInfo &MRI,
46 MCAsmBackend *createAMDGPUAsmBackend(const Target &T, const MCRegisterInfo &MRI,
|
| R600MCCodeEmitter.cpp | 37 const MCRegisterInfo &MRI;
40 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCRegisterInfo &mri)
41 : MCII(mcii), MRI(mri) { }
83 const MCRegisterInfo &MRI,
85 return new R600MCCodeEmitter(MCII, MRI);
158 return MRI.getEncodingValue(reg) >> HW_CHAN_SHIFT;
162 return MRI.getEncodingValue(RegNo) & HW_REG_MASK;
171 return MRI.getEncodingValue(MO.getReg());
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPeephole.cpp | 83 const auto &MRI = MF.getRegInfo();
86 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg());
108 const auto &MRI = MF.getRegInfo();
110 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg());
120 // Check if MRI has only one non dbg use, which is Root
121 if (MRI.hasOneNonDBGUse(Prev.getOperand(0).getReg())) {
144 const auto &MRI = MF.getRegInfo();
145 if (MRI.use_empty(NVPTX::VRFrame)) {
146 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) {
|
