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  /external/llvm/test/CodeGen/AMDGPU/
no-shrink-extloads.ll 3 declare i32 @llvm.r600.read.tidig.x() nounwind readnone
25 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
47 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
69 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
91 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
114 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
138 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
161 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
184 %tid = call i32 @llvm.r600.read.tidig.x() nounwind readnone
swizzle-export.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
71 call void @llvm.R600.store.swizzle(<4 x float> %59, i32 60, i32 1)
76 call void @llvm.R600.store.swizzle(<4 x float> %63, i32 0, i32 2)
81 call void @llvm.R600.store.swizzle(<4 x float> %67, i32 1, i32 2)
86 call void @llvm.R600.store.swizzle(<4 x float> %71, i32 2, i32 2)
91 call void @llvm.R600.store.swizzle(<4 x float> %75, i32 3, i32 2)
114 call void @llvm.R600.store.swizzle(<4 x float> %12, i32 60, i32 1)
119 call void @llvm.R600.store.swizzle(<4 x float> %16, i32 0, i32 2)
126 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
fmin_legacy.f64.ll 3 declare i32 @llvm.r600.read.tidig.x() #1
18 %tid = call i32 @llvm.r600.read.tidig.x() #1
33 %tid = call i32 @llvm.r600.read.tidig.x() #1
48 %tid = call i32 @llvm.r600.read.tidig.x() #1
63 %tid = call i32 @llvm.r600.read.tidig.x() #1
shl_add_ptr.ll 10 declare i32 @llvm.r600.read.tidig.x() #1
23 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
43 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
59 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
77 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
93 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
108 ; %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
123 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
138 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #1
152 %tid.x = tail call i32 @llvm.r600.read.tidig.x() #
    [all...]
add_i64.ll 4 declare i32 @llvm.r600.read.tidig.x() readnone
10 %tid = call i32 @llvm.r600.read.tidig.x() readnone
62 %tid = call i32 @llvm.r600.read.tidig.x() readnone
drop-mem-operand-move-smrd.ll 15 %tid = tail call i32 @llvm.r600.read.tidig.x() #1
45 declare i32 @llvm.r600.read.tidig.x() #1
48 declare i32 @llvm.r600.read.tgid.x() #1
jump-address.ll 1 ;RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
39 call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
50 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
llvm.AMDGPU.cube.ll 2 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s
42 call void @llvm.R600.store.swizzle(<4 x float> %30, i32 0, i32 0)
55 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
local-memory-two-objects.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck --check-prefix=EG %s
40 %x.i = call i32 @llvm.r600.read.tidig.x() #0
60 declare i32 @llvm.r600.read.tidig.x() #0
move-to-valu-atomicrmw.ll 10 declare i32 @llvm.r600.read.tidig.x() #1
15 %tid = call i32 @llvm.r600.read.tidig.x()
35 %tid = call i32 @llvm.r600.read.tidig.x()
r600-infinite-loop-bug-while-reorganizing-vector.ll 1 ;RUN: llc < %s -march=r600 -mcpu=cayman
42 call void @llvm.R600.store.swizzle(<4 x float> %38, i32 0, i32 0)
55 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
rv7x0_count3.ll 1 ; RUN: llc < %s -march=r600 -show-mc-encoding -mcpu=rv710 | FileCheck %s
33 call void @llvm.R600.store.swizzle(<4 x float> %27, i32 0, i32 2)
39 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
schedule-fs-loop.ll 1 ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
41 call void @llvm.R600.store.swizzle(<4 x float> %24, i32 0, i32 0)
53 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
schedule-if.ll 1 ;RUN: llc < %s -march=r600 -mcpu=cayman -stress-sched -verify-misched -verify-machineinstrs
35 call void @llvm.R600.store.swizzle(<4 x float> %19, i32 0, i32 0)
46 declare void @llvm.R600.store.swizzle(<4 x float>, i32, i32)
mad_int24.ll 1 ; RUN: llc < %s -march=r600 -mcpu=redwood | FileCheck %s --check-prefix=EG --check-prefix=FUNC
2 ; RUN: llc < %s -march=r600 -mcpu=cayman | FileCheck %s --check-prefix=CM --check-prefix=FUNC
v_cndmask.ll 4 declare i32 @llvm.r600.read.tidig.x() #1
12 %idx = call i32 @llvm.r600.read.tidig.x() #1
commute_modifiers.ll 3 declare i32 @llvm.r600.read.tidig.x() #1
12 %tid = call i32 @llvm.r600.read.tidig.x() #1
26 %tid = call i32 @llvm.r600.read.tidig.x() #1
41 %tid = call i32 @llvm.r600.read.tidig.x() #1
57 %tid = call i32 @llvm.r600.read.tidig.x() #1
72 %tid = call i32 @llvm.r600.read.tidig.x() #1
89 %tid = call i32 @llvm.r600.read.tidig.x() #1
106 %tid = call i32 @llvm.r600.read.tidig.x() #1
125 %tid = call i32 @llvm.r600.read.tidig.x() #1
143 %tid = call i32 @llvm.r600.read.tidig.x() #
    [all...]
  /external/llvm/include/llvm/IR/
IntrinsicsAMDGPU.td 10 // This file defines all of the R600-specific intrinsics.
14 let TargetPrefix = "r600" in {
44 } // End TargetPrefix = "r600"
  /external/mesa3d/src/gallium/targets/egl-static/
egl_pipe.c 41 /* for r600 */
42 #include "r600/r600_public.h"
191 else if (strcmp(name, "r600") == 0)
  /external/llvm/lib/Target/AMDGPU/
R600MachineScheduler.h 1 //===-- R600MachineScheduler.h - R600 Scheduler Interface -*- C++ -*-------===//
11 /// \brief R600 Machine Scheduler interface
R600Schedule.td 1 //===-- R600Schedule.td - R600 Scheduling definitions ------*- tablegen -*-===//
10 // R600 has a VLIW architecture. On pre-cayman cards there are 5 instruction
  /external/mesa3d/include/pci_ids/
r600_pci_ids.h 1 CHIPSET(0x9400, R600_9400, R600)
2 CHIPSET(0x9401, R600_9401, R600)
3 CHIPSET(0x9402, R600_9402, R600)
4 CHIPSET(0x9403, R600_9403, R600)
5 CHIPSET(0x9405, R600_9405, R600)
6 CHIPSET(0x940A, R600_940A, R600)
7 CHIPSET(0x940B, R600_940B, R600)
8 CHIPSET(0x940F, R600_940F, R600)
  /external/mesa3d/src/gallium/
SConscript 35 'drivers/r600/SConscript',
158 'targets/dri-r600/SConscript',
  /external/mesa3d/src/gallium/drivers/radeon/
R600ISelLowering.h 1 //===-- R600ISelLowering.h - R600 DAG Lowering Interface -*- C++ -*--------===//
10 // R600 DAG Lowering interface definition
R600RegisterInfo.h 1 //===-- R600RegisterInfo.h - R600 Register Info Interface ------*- C++ -*--===//
35 /// R600 reg class that is equivalent to the given AMDIL reg class.

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