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  /external/llvm/test/Transforms/CodeGenPrepare/X86/
select.ll 132 %div1 = sdiv i32 %a, %b
133 %div2 = sdiv i32 %b, %a
  /external/llvm/test/Transforms/InstSimplify/
undef.ll 62 %r = sdiv i64 undef, 1
174 %b = sdiv i32 %a, 0
compare.ll 617 %A = sdiv i32 %X, 1000000
854 %div = sdiv i32 2, %a
996 %div = sdiv i32 -2147483648, %a
1001 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i32 -2147483648, %a
1007 %div = sdiv i64 %a, -8589934592
1012 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 %a, -8589934592
1018 %div = sdiv i64 %a, -1
1023 ; CHECK-NEXT: [[DIV:%.*]] = sdiv i64 %a, -1
  /external/llvm/lib/Target/X86/
X86TargetTransformInfo.cpp 98 if (ISD == ISD::SDIV &&
121 { ISD::SDIV, MVT::v16i16, 6 }, // vpmulhw sequence
123 { ISD::SDIV, MVT::v8i32, 15 }, // vpmuldq sequence
224 { ISD::SDIV, MVT::v32i8, 32*20 },
225 { ISD::SDIV, MVT::v16i16, 16*20 },
226 { ISD::SDIV, MVT::v8i32, 8*20 },
227 { ISD::SDIV, MVT::v4i64, 4*20 },
273 { ISD::SDIV, MVT::v8i16, 6 }, // pmulhw sequence
275 { ISD::SDIV, MVT::v4i32, 19 }, // pmuludq sequence
282 if (ISD == ISD::SDIV && LT.second == MVT::v4i32 && ST->hasSSE41()
    [all...]
  /external/llvm/lib/Transforms/InstCombine/
InstCombineMulDivRem.cpp 10 // This file implements the visit functions for mul, fmul, sdiv, udiv, fdiv,
311 BO->getOpcode() != Instruction::SDiv)) {
319 BO->getOpcode() == Instruction::SDiv)) {
323 if (PossiblyExactOperator *SDiv = dyn_cast<PossiblyExactOperator>(BO))
324 if (SDiv->isExact()) {
786 /// instructions (udiv and sdiv). It is called by the visitors to those integer
808 bool IsSigned = I.getOpcode() == Instruction::SDiv;
885 bool isSigned = I.getOpcode() == Instruction::SDiv;
909 bool isSigned = I.getOpcode() == Instruction::SDiv;
    [all...]
  /external/llvm/lib/Transforms/Utils/
IntegerDivision.cpp 101 /// code generated, e.g. at the sdiv instruction. This will generate a udiv in
437 assert((Div->getOpcode() == Instruction::SDiv ||
453 if (Div->getOpcode() == Instruction::SDiv) {
591 assert((Div->getOpcode() == Instruction::SDiv ||
617 if (Div->getOpcode() == Instruction::SDiv) {
641 assert((Div->getOpcode() == Instruction::SDiv ||
667 if (Div->getOpcode() == Instruction::SDiv) {
BypassSlowDivision.cpp 233 bool UseDivOp = Opcode == Instruction::SDiv || Opcode == Instruction::UDiv;
235 bool UseSignedOp = Opcode == Instruction::SDiv ||
  /external/llvm/lib/Target/Sparc/
SparcISelDAGToDAG.cpp 339 case ISD::SDIV:
350 if (N->getOpcode() == ISD::SDIV) {
362 unsigned Opcode = N->getOpcode() == ISD::SDIV ? SP::SDIVrr : SP::UDIVrr;
  /external/llvm/test/CodeGen/NVPTX/
arithmetic-int.ll 35 %ret = sdiv i64 %a, %b
132 %ret = sdiv i32 %a, %b
225 %ret = sdiv i16 %a, %b
  /external/llvm/test/Transforms/InstCombine/
sub.ll 151 %X = sdiv i32 %A, 1123
155 ; CHECK: %Y = sdiv i32 %A, -1123
163 %C = sdiv i32 %B, 1234
167 ; CHECK: %C = sdiv i32 %B, 1234
450 %div = sdiv <2 x i32> %A, <i32 -2147483648, i32 -2147483648>
460 %div = sdiv i32 %A, -2147483648
getelementptr.ll 849 %shr = sdiv i64 %sub, 7
865 %shr = sdiv i64 %sub, 7
877 %sdiv = sdiv i64 %sub, %N
878 %gep = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %sdiv
884 ; CHECK-NEXT: [[SDIV:%.*]] = sdiv i64 [[SUB]], %N
885 ; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds %struct.C, %struct.C* %c2, i64 %sdiv
  /frameworks/compile/mclinker/lib/Target/ARM/
ARMELFAttributeData.cpp 306 // 2 means the code was permitted to use SDIV/UDIV in anyway.
659 // 0: The code was permitted to use SDIV and UDIV in the Thumb ISA on v7-R or
661 // 1: The code was not permitted to use SDIV and UDIV.
662 // 2: The code was explicitly permitted to use SDIV and UDIV.
    [all...]
  /external/llvm/test/CodeGen/ARM/
2010-06-21-LdStMultipleBug.ll 44 %iftmp.40.0.neg = sdiv i32 0, -2 ; <i32> [#uses=2]
50 %iftmp.41.0.neg = sdiv i32 %iftmp.41.0.in, -2 ; <i32> [#uses=3]
2007-05-14-RegScavengerAssert.ll 22 %tmp68 = sdiv i64 0, 0 ; <i64> [#uses=1]
  /external/llvm/test/CodeGen/Mips/msa/
llvm-stress-s3926023935.ll 41 %B15 = sdiv i64 334618, -1
98 %B51 = sdiv i64 %E19, 463132
llvm-stress-s3997499501.ll 60 %B22 = sdiv <4 x i64> %Shuff7, zeroinitializer
140 %B69 = sdiv <16 x i64> <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>, <i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1, i64 -1>
3r-d.ll 100 %2 = sdiv <16 x i8> %0, %1
116 %2 = sdiv <8 x i16> %0, %1
132 %2 = sdiv <4 x i32> %0, %1
148 %2 = sdiv <2 x i64> %0, %1
  /external/llvm/test/CodeGen/X86/
2008-04-28-CoalescerBug.ll 99 %tmp13337 = sdiv i64 0, 0 ; <i64> [#uses=1]
112 %tmp13358 = sdiv i64 %tmp13354, %tmp13357 ; <i64> [#uses=1]
  /external/llvm/test/Transforms/LoopVectorize/
if-conversion.ll 132 %cond = phi i32 [ sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 0), i32** @c) to i32)), %cond.false ], [ 0, %for.body ]
159 %cond.1 = or i32 %inc3, sdiv (i32 1, i32 zext (i1 icmp eq (i32** getelementptr inbounds ([1 x i32*], [1 x i32*]* @a, i64 0, i64 1), i32** @c) to i32))
  /external/llvm/include/llvm/IR/
Instruction.def 131 HANDLE_BINARY_INST(18, SDiv , BinaryOperator)
  /external/llvm/lib/Target/WebAssembly/
WebAssemblyInstrInteger.td 26 defm DIV_S : BinaryInt<sdiv, "div_s">;
  /external/llvm/test/CodeGen/AArch64/
arm64-ccmp.ll 105 ; The sdiv/udiv instructions do not trap when the divisor is zero, so they are
109 ; CHECK: sdiv [[DIVRES:w[0-9]+]], w1, w0
121 %div = sdiv i32 %b, %a
170 %div = sdiv i32 %b, %a
arm64-fast-isel.ll 110 %sub.ptr.div = sdiv exact i64 %arg, 8
arm64-misched-basic-A57.ll 88 %div = sdiv i32 %4, %5
  /external/llvm/test/CodeGen/AMDGPU/
schedule-fs-loop-nested.ll 11 %5 = sdiv i32 %4, 4

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