| /external/libunwind/doc/ |
| libunwind-dynamic.tex | 337 spills register \Var{reg} to a frame-pointer-relative location. The
343 spills register \Var{reg} to a stack-pointer-relative location. The
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 157 /// Creates an ordered list of EH info register 'spills'.
579 // Reserve slots close to SP or frame pointer for Scavenging spills.
|
| /external/llvm/test/CodeGen/X86/ |
| misched-matmul.ll | 6 ; We can further reduce spills in this case with a global register
13 ; CHECK: 23 regalloc - Number of spills inserted
|
| pmul.ll | 296 ; Use a call to force spills.
345 ; Use a call to force spills.
|
| pr18846.ll | 7 ; Test for unnecessary repeated spills due to eliminateRedundantSpills failing
|
| /art/compiler/utils/x86_64/ |
| assembler_x86_64_test.cc | [all...] |
| /bionic/libc/arch-mips/bionic/ |
| setjmp.S | 222 REG_L gp, GPOFF(sp) # restore spills
|
| /bootable/recovery/ |
| fuse_sideload.cpp | 345 // Second case: the read spills over into the next block.
|
| /external/clang/docs/ |
| DataFlowSanitizerDesign.rst | 76 set, causing register spills and hampering performance.
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 188 // frame, it's less likely to have lots of spills and callee saved
|
| AArch64FrameLowering.cpp | 751 // Issue sequence of non-sp increment and pi sp spills for cs regs. The
758 // pre-increment spills like stp xi,xj,[sp,#-16]!
[all...] |
| AArch64AdvSIMDScalarPass.cpp | 22 // register copies rather than spills. As such, a similar approach is
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 801 // Skip the rest if this is a leaf function & all spills fit in the Red Zone.
[all...] |
| /external/llvm/test/CodeGen/XCore/ |
| epilogue_prologue.ll | 17 ; !FP + small frame: no spills = no stack adjustment needed
|
| /external/v8/src/compiler/ |
| schedule.cc | 366 // that spills only in deferred blocks inserts its spill in the block, but
|
| register-allocator.h | 559 // and instead let the LiveRangeConnector perform the spills within the
560 // deferred blocks. If so, we insert here spills for non-spilled ranges
[all...] |
| /external/v8/test/unittests/compiler/ |
| register-allocator-unittest.cc | 680 // TODO(mtrofin): at the moment, the linear allocator spills var1 and var2,
|
| /external/valgrind/docs/internals/ |
| register-uses.txt | 132 holding the address for F32/F64 spills, since the VFP load/store
|
| /external/llvm/lib/CodeGen/ |
| RegAllocPBQP.cpp | 664 // Set to true if we have any spills
746 // This process is continued till no more spills are generated.
|
| MachineLICM.cpp | 54 SinkInstsToAvoidSpills("sink-insts-to-avoid-spills",
56 "loops to avoid register spills"),
711 /// register spills caused by register pressure if there is little to no
[all...] |
| /external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
| ivchain-ARM.ll | 80 ; no spills
207 ; mentioned. Most importantly, there should be no spills or reloads!
|
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 36 SpillAlignedNEONRegs("align-neon-spills", cl::Hidden, cl::init(true),
37 cl::desc("Align ARM NEON spills in prolog and epilog"));
377 // This is a DPR. Exclude the aligned DPRCS2 spills.
495 // Adjust SP after all the callee-save spills.
[all...] |
| /art/runtime/arch/arm/ |
| quick_entrypoints_arm.S | [all...] |
| /external/libunwind/src/ia64/ |
| unwind_i.h | 448 unsigned int any_spills : 1; /* got any register spills? */
|
| /external/llvm/docs/ |
| StackMaps.rst | 480 while Indirect locations handle register spills.
|
