| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInteger.td | 28 defm REM_S : BinaryInt<srem, "rem_s">;
|
| /external/llvm/test/CodeGen/PowerPC/ |
| ctrloop-i64.ll | 81 %conv = srem i64 %x.05, %d
|
| /external/llvm/test/CodeGen/X86/ |
| i386-shrink-wrapping.ll | 102 %rem = srem i32 %tmp1, %add
|
| norex-subreg.ll | 32 %rem = srem i32 %conv3, 15
|
| 2011-01-24-DbgValue-Before-Use.ll | 32 %rem = srem i64 %a.addr.0, %b.addr.0, !dbg !21
|
| vselect-avx.ll | 76 %tmp6 = srem <4 x i32> %induction30, <i32 3, i32 3, i32 3, i32 3>
|
| /external/llvm/utils/emacs/ |
| llvm-mode.el | 43 `(,(regexp-opt '("add" "sub" "mul" "sdiv" "udiv" "urem" "srem" "and" "or" "xor"
|
| /external/llvm/utils/vim/syntax/ |
| llvm.vim | 33 syn keyword llvmStatement sext sge sgt shl shufflevector sitofp sle slt srem
|
| /external/llvm/test/CodeGen/ARM/ |
| vector-promotion.ll | 185 ; IR-NORMAL-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 [[EXTRACT]], 7
187 ; IR-STRESS-NEXT: [[DIV:%[a-zA-Z_0-9-]+]] = srem <2 x i32> [[LOAD]], <i32 7, i32 7>
195 %out = srem i32 %extract, 7
260 ; IR-BOTH-NEXT: [[RES:%[a-zA-Z_0-9-]+]] = srem i32 7, [[EXTRACT]]
266 %out = srem i32 7, %extract
|
| /external/mesa3d/src/gallium/drivers/radeon/ |
| AMDILISelLowering.cpp | 118 // TODO: Implement custom UREM/SREM routines
119 setOperationAction(ISD::SREM, VT, Expand);
179 setOperationAction(ISD::SREM, MVT::v2i64, Expand);
655 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
673 LHS = DAG.getNode(ISD::SREM, DL, INTTY, LHS, RHS);
|
| /external/llvm/include/llvm/ADT/ |
| APSInt.h | 104 *this = srem(RHS);
117 return IsUnsigned ? APSInt(urem(RHS), true) : APSInt(srem(RHS), false);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreLowerThreadLocal.cpp | 96 case Instruction::SRem:
|
| /external/llvm/test/CodeGen/Mips/ |
| mips64instrs.ll | 164 %rem = srem i64 %a, %b
|
| /external/llvm/test/CodeGen/WebAssembly/ |
| i32.ll | 68 %a = srem i32 %x, %y
|
| i64.ll | 68 %a = srem i64 %x, %y
|
| /external/llvm/test/Other/ |
| lint.ll | 41 %sr = srem i32 2, 0
|
| /external/llvm/test/Transforms/InstSimplify/ |
| reassociate.ll | 116 %rem = srem i32 %x, %y
|
| undef.ll | 76 %r = srem i64 undef, 1
|
| /external/llvm/utils/kate/ |
| llvm.xml | 129 <item> srem </item>
|
| /external/llvm/unittests/IR/ |
| ConstantsTest.cpp | 92 // @s = constant i1 srem(i1 -1, i1 1) ; overflow
100 // @u = constant i1 srem(i1 1, i1 -1) ; overflow
224 CHECK(ConstantExpr::getSRem(P0, P0), "srem i32 " P0STR ", " P0STR);
|
| /external/llvm/test/Transforms/InstCombine/ |
| vec_shuffle.ll | 410 ; for an srem operation. This is not a valid optimization because it may cause a trap
417 ; CHECK-NEXT: %retval = srem <4 x i32> %splat1, %splat2
420 %retval = srem <4 x i32> %splat1, %splat2
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 166 case Instruction::SRem:
|
| /external/llvm/test/CodeGen/Generic/ |
| print-arith-int.ll | 36 %rem_r = srem i32 %b, %a ; <i32> [#uses=1]
|
| /external/llvm/test/CodeGen/Mips/msa/ |
| arithmetic.ll | 607 %3 = srem <16 x i8> %1, %2
623 %3 = srem <8 x i16> %1, %2
639 %3 = srem <4 x i32> %1, %2
655 %3 = srem <2 x i64> %1, %2
|
| llvm-stress-s1935737938.ll | 78 %B43 = srem i8 %L5, %L39
|
