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  /external/llvm/test/CodeGen/AMDGPU/
store.ll 88 %0 = trunc <2 x i32> %in to <2 x i8>
103 %0 = trunc <2 x i32> %in to <2 x i16>
119 %0 = trunc <4 x i32> %in to <4 x i8>
151 %0 = trunc <4 x i32> %in to <4 x i16>
191 %0 = trunc i64 %in to i8
201 %0 = trunc i64 %in to i16
322 %0 = trunc i64 %in to i8
332 %0 = trunc i64 %in to i16
  /external/llvm/test/CodeGen/Hexagon/
adde.ll 28 %tmp1617 = trunc i128 %tmp15 to i64
31 %tmp2122 = trunc i128 %tmp21 to i64
  /external/llvm/test/CodeGen/Hexagon/vect/
vect-shuffle.ll 31 %4 = trunc <2 x i32> %add33p_vec to <2 x i16>
32 %5 = trunc <2 x i32> %add33p_vec48 to <2 x i16>
vect-store-v2i16.ll 2 ; Used to fail with: "Cannot select: 0x3bab680: ch = store <ST4[%lsr.iv522525], trunc to v2i16>
47 %1 = trunc <2 x i32> %shr100293p_vec to <2 x i16>
  /external/llvm/test/CodeGen/PowerPC/
loop-data-prefetch-inner.ll 34 %trunc.resume.val = phi i64 [ 0, %vector.memcheck ], [ 1600, %vector.body ]
38 %indvars.iv = phi i64 [ %indvars.iv.next, %for.body3 ], [ %trunc.resume.val, %middle.block ]
rounding-ops.ll 91 %call = tail call double @trunc(double %x) nounwind readnone
100 declare double @trunc(double) nounwind readnone
  /external/llvm/test/CodeGen/WebAssembly/
load-store-i1.ll 55 %t = trunc i32 %v to i1
65 %t = trunc i64 %v to i1
signext-zeroext.ll 38 %s = trunc i32 %t to i8
56 %s = trunc i32 %t to i8
  /external/llvm/test/CodeGen/X86/
2008-02-25-X86-64-CoalescerBug.ll 30 %tmp.135 = trunc i64 %tmp63 to i32 ; <i32> [#uses=1]
37 %tmp8384 = trunc i32 %DD to i16 ; <i16> [#uses=1]
2009-08-23-SubRegReuseUndo.ll 16 %2 = trunc i32 %1 to i8 ; <i8> [#uses=1]
20 %6 = trunc i32 %5 to i8 ; <i8> [#uses=1]
2012-02-29-CoalescerBug.ll 31 %conv = trunc i64 %2 to i16
41 %p1.lobit.i8.tr = trunc i64 %p1.lobit.i8 to i16
peep-test-3.ll 55 %t = trunc i32 %3 to i8
68 ; Just like @and, but without the trunc+store. This should use a testb
sink-out-of-loop.ll 31 %lftr.wideiv32 = trunc i64 %iv.next.i to i32
48 %lftr.wideiv = trunc i64 %iv.next to i32
  /external/llvm/test/Instrumentation/AddressSanitizer/X86/
asm_more_registers_than_available.ll 43 %conv2 = trunc i32 %conv to i8
49 %conv6 = trunc i32 %conv5 to i8
  /external/llvm/test/Transforms/AtomicExpand/ARM/
atomic-expansion-v8.ll 9 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i8
27 ; CHECK: [[OLDVAL:%.*]] = trunc i32 [[OLDVAL32]] to i16
71 ; CHECK: [[NEWLO:%.*]] = trunc i64 [[NEWVAL]] to i32
73 ; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
92 ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i8
130 ; CHECK: [[OLDVAL:%.*]] = trunc i32 %1 to i16
215 ; CHECK: [[NEWLO:%.*]] = trunc i64 %newval to i32
217 ; CHECK: [[NEWHI:%.*]] = trunc i64 [[NEWHI_TMP]] to i32
  /external/llvm/test/Transforms/InstCombine/
2006-05-04-DemandedBitCrash.ll 9 %tmp51392.i1019 = trunc i64 %tmp51391.i1018 to i32 ; <i32> [#uses=2]
13 %tmp18.i1027 = trunc i32 %tmp18.i1026 to i8 ; <i8> [#uses=1]
2012-05-27-Negative-Shift-Crash.ll 17 %conv = trunc i32 %shr to i8
44 %2 = trunc i32 %.lobit to i8
  /external/llvm/test/Transforms/LoopUnroll/
runtime-loop3.ll 30 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
37 %lftr.wideiv18 = trunc i64 %indvars.iv.next17 to i32
  /external/llvm/test/Transforms/LoopVectorize/
2012-10-22-isconsec.ll 29 %6 = trunc i64 %indvars.iv.next to i32
48 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
calloc.ll 31 %sh_prom = trunc i64 %and3 to i32
39 %conv18 = trunc i32 %add17 to i8
float-reduction.ll 19 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
41 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
unroll_novec.ll 38 %4 = trunc i64 %indvars.iv to i32
42 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  /external/llvm/test/Transforms/LoopVectorize/ARM/
gcc-examples.ll 29 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
53 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
width-detect.ll 20 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
43 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
  /external/llvm/test/Transforms/LoopVectorize/X86/
avx1.ll 20 %lftr.wideiv = trunc i64 %indvars.iv.next to i32
43 %lftr.wideiv = trunc i64 %indvars.iv.next to i32

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