| /external/libhevc/decoder/arm/ |
| ihevcd_itrans_recon_dc_luma.s | 93 vld1.8 d2,[r7],r2
94 vld1.8 d3,[r7],r2
95 vld1.8 d4,[r7],r2
96 vld1.8 d5,[r7],r2
98 vld1.8 d6,[r7],r2
99 vld1.8 d7,[r7],r2
100 vld1.8 d8,[r7],r2
101 vld1.8 d9,[r7]
157 vld1.8 d2,[r0],r2
158 vld1.8 d3,[r0],r
[all...] |
| /external/llvm/test/CodeGen/AArch64/ |
| arm64-neon-copyPhysReg-tuple.ll | 12 %vld1 = tail call { <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld2lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, i64 1, i32* %b)
13 %vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32> } %vld1, 0
14 ret <4 x i32> %vld1.fca.0.extract
26 %vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld3lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, i64 1, i32* %b)
27 %vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32> } %vld1, 0
28 ret <4 x i32> %vld1.fca.0.extract
41 %vld1 = tail call { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } @llvm.aarch64.neon.ld4lane.v4i32.p0i32(<4 x i32> %extract, <4 x i32> <i32 -1, i32 -1, i32 -1, i32 -1>, <4 x i32> %c, <4 x i32> %c, i64 1, i32* %b)
42 %vld1.fca.0.extract = extractvalue { <4 x i32>, <4 x i32>, <4 x i32>, <4 x i32> } %vld1,
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfVer4x4_unsafe_s.s | 87 VLD1 dSrc0, [pSrc], srcStep ;// [a0 a1 a2 a3 .. ]
89 VLD1 dSrc1, [pSrc], srcStep ;// [b0 b1 b2 b3 .. ]
91 VLD1 dSrc5, [Temp], srcStep
93 VLD1 dSrc2, [pSrc], srcStep ;// [c0 c1 c2 c3 .. ]
95 VLD1 dSrc3, [pSrc], srcStep
97 VLD1 dSrc6, [Temp], srcStep ;// TeRi
99 VLD1 dSrc4, [pSrc], srcStep
100 VLD1 dSrc7, [Temp], srcStep ;// TeRi
103 VLD1 dSrc8, [Temp], srcStep ;// TeRi
108 ; VLD1 dSrc6, [Temp], srcSte
[all...] |
| omxVCM4P10_FilterDeblockingChroma_VerEdge_I_s.s | 129 VLD1 {dAlpha[]}, [pAlpha]!
131 VLD1 {dBeta[]}, [pBeta]!
159 VLD1 dRow0, [pSrcDst], step
161 VLD1 dRow1, [pTmp], step
162 VLD1 dRow2, [pSrcDst], step
163 VLD1 dRow3, [pTmp], step
164 VLD1 dRow4, [pSrcDst], step
165 VLD1 dRow5, [pTmp], step
166 VLD1 dRow6, [pSrcDst], step
167 VLD1 dRow7, [pTmp], ste
[all...] |
| omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.s | 175 VLD1 {dAlpha[]}, [pAlpha_0]
177 VLD1 {dBeta[]}, [pBeta_0]
203 VLD1 dP_3, [pSrcDst], step
204 VLD1 dP_2, [pTmp], step
205 VLD1 dP_1, [pSrcDst], step
206 VLD1 dP_0, [pTmp], step
207 VLD1 dQ_0, [pSrcDst], step
209 VLD1 dQ_1, [pTmp]
211 VLD1 dQ_2, [pSrcDst], srcdstStep
230 VLD1 dQ_3, [pSrcDst
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm/ |
| h264bsdWriteMacroblock.s | 100 VLD1 {qRow0, qRow1}, [data]!
102 VLD1 {qRow2, qRow3}, [data]!
105 VLD1 {qRow4, qRow5}, [data]!
107 VLD1 {qRow6, qRow7}, [data]!
109 VLD1 {qRow8, qRow9}, [data]!
111 VLD1 {qRow10, qRow11}, [data]!
113 VLD1 {qRow12, qRow13}, [data]!
115 VLD1 {qRow14, qRow15}, [data]!
118 VLD1 {qRow0, qRow1}, [data]! ;cb rows 0,1,2,3
120 VLD1 {qRow2, qRow3}, [data]! ;cb rows 4,5,6,
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/ |
| h264bsdWriteMacroblock.S | 102 VLD1.8 {qRow0, qRow1}, [data]!
104 VLD1.8 {qRow2, qRow3}, [data]!
107 VLD1.8 {qRow4, qRow5}, [data]!
109 VLD1.8 {qRow6, qRow7}, [data]!
111 VLD1.8 {qRow8, qRow9}, [data]!
113 VLD1.8 {qRow10, qRow11}, [data]!
115 VLD1.8 {qRow12, qRow13}, [data]!
117 VLD1.8 {qRow14, qRow15}, [data]!
120 VLD1.8 {qRow0, qRow1}, [data]! ;//cb rows 0,1,2,3
122 VLD1.8 {qRow2, qRow3}, [data]! ;//cb rows 4,5,6,
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_inter_pred_chroma_copy_w16out.s | 132 vld1.8 {d0},[r0] @vld1_u8(pu1_src_tmp)
138 vld1.8 {d22},[r5],r2 @vld1_u8(pu1_src_tmp)
143 vld1.8 {d24},[r5],r2 @vld1_u8(pu1_src_tmp)
148 vld1.8 {d26},[r5],r2 @vld1_u8(pu1_src_tmp)
173 vld1.8 {d0},[r0] @vld1_u8(pu1_src_tmp)
179 vld1.8 {d22},[r5],r2 @vld1_u8(pu1_src_tmp)
184 vld1.8 {d24},[r5],r2 @vld1_u8(pu1_src_tmp)
208 vld1.8 {d8},[r0]! @vld1_u8(pu1_src_tmp)
209 vld1.8 {d10},[r6],r2 @vld1_u8(pu1_src_tmp)
210 vld1.8 {d12},[r6],r2 @vld1_u8(pu1_src_tmp
[all...] |
| ihevc_itrans_recon_16x16.s | 147 vld1.16 {d0,d1,d2,d3},[r14] @//d0,d1 are used for storing the constant data
222 vld1.16 d10,[r0],r6
223 vld1.16 d11,[r9],r6
224 vld1.16 d6,[r0],r10
225 vld1.16 d7,[r9],r10
229 vld1.16 d4,[r0],r6
230 vld1.16 d5,[r9],r6
231 vld1.16 d8,[r0],r8
232 vld1.16 d9,[r9],r8
305 vld1.16 d10,[r0],r
[all...] |
| ihevc_intra_pred_chroma_mode_27_to_33.s | 145 vld1.8 {d3},[r6] @loads the row value
163 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
167 vld1.8 {d9},[r10] @(i row)ref_main_idx_1
174 vld1.8 {d12},[r12],r11 @(ii)ref_main_idx
177 vld1.8 {d13},[r12] @(ii)ref_main_idx_1
189 vld1.8 {d16},[r10],r11 @(iii)ref_main_idx
192 vld1.8 {d17},[r10] @(iii)ref_main_idx_1
195 vld1.8 {d20},[r12],r11 @(iv)ref_main_idx
198 vld1.8 {d21},[r12] @(iv)ref_main_idx_1
214 vld1.8 {d8},[r10],r11 @(v)ref_main_id
[all...] |
| ihevc_intra_pred_luma_mode_27_to_33.s | 149 vld1.8 {d3},[r6] @loads the row value
166 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
170 vld1.8 {d9},[r10] @(i row)ref_main_idx_1
177 vld1.8 {d12},[r12],r11 @(ii)ref_main_idx
180 vld1.8 {d13},[r12] @(ii)ref_main_idx_1
192 vld1.8 {d16},[r10],r11 @(iii)ref_main_idx
195 vld1.8 {d17},[r10] @(iii)ref_main_idx_1
198 vld1.8 {d20},[r12],r11 @(iv)ref_main_idx
201 vld1.8 {d21},[r12] @(iv)ref_main_idx_1
216 vld1.8 {d8},[r10],r11 @(v)ref_main_id
[all...] |
| ihevc_inter_pred_chroma_vert_w16inp.s | 113 vld1.8 {d0},[r4] @loads pi1_coeff
138 vld1.16 {d0},[r4]! @loads pu1_src
141 vld1.16 {d2},[r0],r2 @loads pi2_src
143 vld1.16 {d3},[r0],r2 @loads pi2_src
145 vld1.16 {d6},[r0],r2
147 vld1.16 {d2},[r0]
183 vld1.16 {d0},[r4]! @loads pu1_src
184 vld1.16 {d1},[r0],r2 @loads pi2_src
186 vld1.16 {d2},[r0],r2 @loads pi2_src
188 vld1.16 {d3},[r0],r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| vp8_subpixelvariance16x16_neon.asm | 47 vld1.s32 {d31}, [r2] ;load first_pass filter
52 vld1.u8 {d2, d3, d4}, [r0], r1 ;load src data
54 vld1.u8 {d5, d6, d7}, [r0], r1
57 vld1.u8 {d8, d9, d10}, [r0], r1
60 vld1.u8 {d11, d12, d13}, [r0], r1
109 vld1.u8 {d2, d3, d4}, [r0], r1 ;load src data
111 vld1.u8 {d5, d6, d7}, [r0], r1
114 vld1.u8 {d8, d9, d10}, [r0], r1
116 vld1.u8 {d11, d12, d13}, [r0], r1
121 vld1.u8 {d14, d15, d16}, [r0], r
[all...] |
| /external/libmpeg2/common/arm/ |
| impeg2_inter_pred.s | 109 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
113 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
115 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
117 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
119 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
121 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
123 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
125 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
127 vld1.8 {d0, d1}, [r4], r2 @Load and increment src
129 vld1.8 {d0, d1}, [r4], r2 @Load and increment sr
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| spill-q.ll | 10 declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly
16 ; CHECK: vld1.64 {{.*}}sp:128
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %vecptr, i32 1) nounwind ; <<4 x float>> [#uses=1]
23 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwin
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| thumb2-spill-q.ll | 10 declare <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8*, i32) nounwind readonly
16 ; CHECK: vld1.64 {{.*}}[{{.*}}:128]
21 %0 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %vecptr, i32 1) nounwind
23 %1 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
25 %2 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind ; <<4 x float>> [#uses=1]
26 %ld3 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
28 %ld4 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
30 %ld5 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
32 %ld6 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwind
34 %ld7 = call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* undef, i32 1) nounwin
[all...] |
| /external/libavc/common/arm/ |
| ih264_inter_pred_luma_horz_qpel_vert_qpel_a9q.s | 140 vld1.32 {q0}, [r7], r2 @ Vector load from src[0_0]
141 vld1.32 {q1}, [r7], r2 @ Vector load from src[1_0]
142 vld1.32 {q2}, [r7], r2 @ Vector load from src[2_0]
143 vld1.32 {q3}, [r7], r2 @ Vector load from src[3_0]
144 vld1.32 {q4}, [r7], r2 @ Vector load from src[4_0]
146 vld1.32 {q5}, [r7], r2 @ Vector load from src[5_0]
147 vld1.32 {q9}, [r6], r2 @ horz row0, col 0
164 vld1.32 {q9}, [r11], r2 @ horz row 0, col 1
177 vld1.32 {q6}, [r7], r2 @ src[6_0]
191 vld1.32 {q9}, [r6], r2 @ horz row 1, col
[all...] |
| ih264_inter_pred_filters_luma_vert_a9q.s | 121 vld1.u32 {q0}, [r0], r2 @ Vector load from src[0_0]
122 vld1.u32 {q1}, [r0], r2 @ Vector load from src[1_0]
123 vld1.u32 {q2}, [r0], r2 @ Vector load from src[2_0]
124 vld1.u32 {q3}, [r0], r2 @ Vector load from src[3_0]
125 vld1.u32 {q4}, [r0], r2 @ Vector load from src[4_0]
127 vld1.u32 {q5}, [r0], r2 @ Vector load from src[5_0]
135 vld1.u32 {q0}, [r0], r2
147 vld1.u32 {q1}, [r0], r2
164 vld1.u32 {q2}, [r0], r2
203 vld1.u32 d0, [r0], r2 @ Vector load from src[0_0
[all...] |
| /bionic/libc/arch-arm/krait/bionic/ |
| memcpy_base.S | 99 vld1.32 {q0, q1}, [r1]!
100 vld1.32 {q2, q3}, [r1]!
114 vld1.32 {q0, q1}, [r1]!
115 vld1.32 {q2, q3}, [r1]!
132 vld1.32 {q0, q1}, [r1]!
133 vld1.32 {q2, q3}, [r1]!
149 vld1.32 {q8, q9}, [r1]!
150 vld1.32 {q10, q11}, [r1]!
161 vld1.32 {q0,q1}, [r1]!
166 vld1.32 {q8}, [r1]
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_loopfilter_neon.asm | 40 vld1.8 {d0[]}, [r2] ; duplicate *blimit
48 vld1.8 {d1[]}, [r3] ; duplicate *limit
49 vld1.8 {d2[]}, [r2] ; duplicate *thresh
55 vld1.u8 {d3}, [r2@64], r1 ; p3
56 vld1.u8 {d4}, [r3@64], r1 ; p2
57 vld1.u8 {d5}, [r2@64], r1 ; p1
58 vld1.u8 {d6}, [r3@64], r1 ; p0
59 vld1.u8 {d7}, [r2@64], r1 ; q0
60 vld1.u8 {d16}, [r3@64], r1 ; q1
61 vld1.u8 {d17}, [r2@64] ; q
[all...] |
| vp9_loopfilter_16_neon.asm | 36 vld1.8 {d0}, [r2] ; load blimit0 to first half q
37 vld1.8 {d2}, [r3] ; load limit0 to first half q
42 vld1.8 {d4}, [r12] ; load thresh0 to first half q
46 vld1.8 {d1}, [r2] ; load blimit1 to 2nd half q
50 vld1.8 {d3}, [r3] ; load limit1 to 2nd half q
51 vld1.8 {d5}, [r12] ; load thresh1 to 2nd half q
57 vld1.u8 {q3}, [r2@64], r1 ; p3
58 vld1.u8 {q4}, [r3@64], r1 ; p2
59 vld1.u8 {q5}, [r2@64], r1 ; p1
60 vld1.u8 {q6}, [r3@64], r1 ; p
[all...] |
| /external/llvm/test/Analysis/BasicAA/ |
| intrinsics.ll | 10 ; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) [[ATTR:#[0-9]+]]
15 %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
17 %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
25 ; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) [[ATTR]]
31 %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
33 %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind
38 declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
|
| /external/boringssl/src/crypto/curve25519/asm/ |
| x25519-asm-arm.S | 67 vld1.8 {d4-d5},[r1]!
68 vld1.8 {d6-d7},[r1]
82 vld1.8 {d8},[r2]
83 vld1.8 {d10},[r2]
85 vld1.8 {d12},[r2]
86 vld1.8 {d14},[r2]
88 vld1.8 {d16},[r2]
90 vld1.8 {d18},[r2]
91 vld1.8 {d20},[r2]
93 vld1.8 {d22},[r2
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_16_neon.asm | 36 vld1.8 {d0}, [r2] ; load blimit0 to first half q
37 vld1.8 {d2}, [r3] ; load limit0 to first half q
42 vld1.8 {d4}, [r12] ; load thresh0 to first half q
46 vld1.8 {d1}, [r2] ; load blimit1 to 2nd half q
50 vld1.8 {d3}, [r3] ; load limit1 to 2nd half q
51 vld1.8 {d5}, [r12] ; load thresh1 to 2nd half q
57 vld1.u8 {q3}, [r2@64], r1 ; p3
58 vld1.u8 {q4}, [r3@64], r1 ; p2
59 vld1.u8 {q5}, [r2@64], r1 ; p1
60 vld1.u8 {q6}, [r3@64], r1 ; p
[all...] |
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| rotate_neon.cc | 43 "vld1.8 {d0}, [%0], %2 \n"
45 "vld1.8 {d1}, [%0], %2 \n"
47 "vld1.8 {d2}, [%0], %2 \n"
49 "vld1.8 {d3}, [%0], %2 \n"
51 "vld1.8 {d4}, [%0], %2 \n"
53 "vld1.8 {d5}, [%0], %2 \n"
55 "vld1.8 {d6}, [%0], %2 \n"
57 "vld1.8 {d7}, [%0] \n"
118 "vld1.32 {d0[0]}, [%0], %2 \n"
120 "vld1.32 {d0[1]}, [%0], %2 \n
[all...] |
