| /external/libyuv/files/source/ |
| rotate_neon.cc | 42 "vld1.8 {d0}, [%0], %2 \n"
44 "vld1.8 {d1}, [%0], %2 \n"
46 "vld1.8 {d2}, [%0], %2 \n"
48 "vld1.8 {d3}, [%0], %2 \n"
50 "vld1.8 {d4}, [%0], %2 \n"
52 "vld1.8 {d5}, [%0], %2 \n"
54 "vld1.8 {d6}, [%0], %2 \n"
56 "vld1.8 {d7}, [%0] \n"
117 "vld1.32 {d0[0]}, [%0], %2 \n"
119 "vld1.32 {d0[1]}, [%0], %2 \n
[all...] |
| /external/libavc/common/arm/ |
| ih264_inter_pred_luma_horz_qpel_vert_hpel_a9q.s | 153 vld1.u32 {q0}, [r0]! @ Vector load from src[0_0]
154 vld1.u32 d12, [r0], r2 @ Vector load from src[0_0]
155 vld1.u32 {q1}, [r0]! @ Vector load from src[1_0]
156 vld1.u32 d13, [r0], r2 @ Vector load from src[1_0]
157 vld1.u32 {q2}, [r0]! @ Vector load from src[2_0]
158 vld1.u32 d14, [r0], r2 @ Vector load from src[2_0]
159 vld1.u32 {q3}, [r0]! @ Vector load from src[3_0]
160 vld1.u32 d15, [r0], r2 @ Vector load from src[3_0]
161 vld1.u32 {q4}, [r0]! @ Vector load from src[4_0]
162 vld1.u32 d16, [r0], r2 @ Vector load from src[4_0
[all...] |
| /external/gemmlowp/meta/ |
| single_thread_gemm.h | 39 "vld1.8 {d0}, [%[source]:64]!\n"
74 "vld1.8 {d0}, [%[source]:64]!\n"
82 "vld1.8 {d0[0]}, [%[source]]\n"
115 "vld1.8 {d0}, [%[source]:64]!\n"
123 "vld1.16 {d0[0]}, [%[source]]\n"
156 "vld1.8 {d0}, [%[source]:64]!\n"
164 "vld1.16 {d0[0]}, [%[source]]!\n"
165 "vld1.8 {d0[2]}, [%[source]]\n"
198 "vld1.8 {d0}, [%[source]:64]!\n"
206 "vld1.32 {d0[0]}, [%[source]]\n
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| vector-load.ll | 8 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
16 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
26 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
34 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
44 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
52 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
62 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
70 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]!
80 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
88 ;CHECK: vld1.8 {{{d[0-9]+}}}, [{{r[0-9]+}}]
[all...] |
| struct_byval_arm_t1_t2.ll | 117 ;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]!
119 ;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]!
122 ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]!
127 ;T1POST-NOT: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]!
139 ;ARM: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]!
142 ;THUMB2: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]!
146 ;NO_NEON-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]!
151 ;T1POST-NOT: vld1.32 {d{{[0-9]+}}, d{{[0-9]+}}}, [r{{.*}}]!
234 ;ARM: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]!
237 ;THUMB2: vld1.32 {d{{[0-9]+}}}, [r{{.*}}]
[all...] |
| vector-extend-narrow.ll | 5 ; CHECK: vld1
23 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
25 ; CHECK: vld1
52 ; Note: vld1 here is reasonably important. Mixing VFP and NEON
54 ; CHECK: vld1
67 ; CHECK: vld1
|
| a15-partial-update.ll | 5 ; The generated code for this test uses a vld1.32 instruction
9 ; vld1.32 instruction. The test checks that a vmov.f64 was not
23 ; The code generated by this test uses a vld1.32 instruction.
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.s | 221 VLD1 {dAlpha[]}, [pAlpha_0]
223 VLD1 {dBeta[]}, [pBeta_0]
251 VLD1 dRow0, [pSrcDst], pTmpStep
252 VLD1 dRow1, [pTmp], pTmpStep
253 VLD1 dRow2, [pSrcDst], pTmpStep
255 VLD1 dRow3, [pTmp], pTmpStep
256 VLD1 dRow4, [pSrcDst], pTmpStep
258 VLD1 dRow5, [pTmp], pTmpStep
259 VLD1 dRow6, [pSrcDst], pTmpStep
260 VLD1 dRow7, [pTmp], pTmpSte
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_YuvToRGB.S | 112 vld1.u8 d20, [r3]!
113 vld1.u8 d21, [r4]!
142 vld1.u8 d17, [r1]!
144 vld1.u8 d21, [r3]!
146 vld1.u32 d20[1], [r3]!
147 vld1.u32 d21[1], [r4]!
152 vld1.u32 d16[1], [r1]!
154 vld1.u32 d20[1], [r3]!
156 vld1.u16 d20[1], [r3]!
157 vld1.u16 d21[1], [r4]
[all...] |
| rsCpuIntrinsics_neon_3DLUT.S | 30 vld1.u8 d16, [r6], r4
31 vld1.u8 d17, [r7], r4
33 vld1.u8 d18, [r6], r5
34 vld1.u8 d19, [r7], r5
46 vld1.u8 d18, [r6]
47 vld1.u8 d19, [r7]
52 vld1.u8 d16, [r6]
53 vld1.u8 d17, [r7]
218 4: vld1.u32 {d0[]}, [r1]
224 vld1.u32 {d0}, [r1]
[all...] |
| rsCpuIntrinsics_neon_ColorMatrix.S | 28 vld1.16 {q2}, [r2]!
29 vld1.16 {q3}, [r2]!
30 vld1.32 {d8[],d9[]}, [r2]!
31 vld1.32 {d10[],d11[]}, [r2]!
32 vld1.32 {d12[],d13[]}, [r2]!
33 vld1.32 {d14[],d15[]}, [r2]!
45 vld1.32 {q4}, [r2]!
46 vld1.32 {q5}, [r2]!
47 vld1.32 {q6}, [r2]!
48 vld1.32 {q7}, [r2]
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_filters_chroma_mode_19_to_25.s | 151 vld1.32 d0,[r1]! @ pu1_ref[two_nt + k]
163 vld1.8 {d0,d1,d2,d3},[r1]!
164 vld1.8 {d4,d5,d6},[r1]!
173 vld1.8 {d0,d1,d2},[r1]!
179 vld1.8 d0,[r1]!
255 vld1.8 {d3},[r6] @loads the row value
273 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
276 vld1.8 {d9},[r10] @(i row)ref_main_idx_1
283 vld1.8 {d12},[r12],r11 @(ii)ref_main_idx
286 vld1.8 {d13},[r12] @(ii)ref_main_idx_
[all...] |
| /external/libmpeg2/common/arm/ |
| ideint_spatial_filter_a9.s | 79 vld1.8 d0, [r0], r2
82 vld1.8 d1, [r5]
86 vld1.8 d2, [r5]
100 vld1.8 d3, [r0], r2
103 vld1.8 d4, [r5]
107 vld1.8 d5, [r5]
211 vld1.u32 d0[0], [r4], r2
212 vld1.u32 d2[0], [r5], r2
214 vld1.u32 d0[1], [r6], r2
215 vld1.u32 d2[1], [r7], r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| sixtappredict4x4_neon.asm | 49 vld1.s32 {q14, q15}, [r2] ;load first_pass filter
60 vld1.u8 {q3}, [r0], r1 ;load first 4-line src data
62 vld1.u8 {q4}, [r0], r1
64 vld1.u8 {q5}, [r0], r1
66 vld1.u8 {q6}, [r0], r1
124 vld1.u8 {q3}, [r0], r1 ;load rest 5-line src data
125 vld1.u8 {q4}, [r0], r1
130 vld1.u8 {q5}, [r0], r1
131 vld1.u8 {q6}, [r0], r1
137 vld1.u8 {q11}, [r0], r
[all...] |
| sixtappredict8x8_neon.asm | 51 vld1.s32 {q14, q15}, [r2] ;load first_pass filter
70 vld1.u8 {q3}, [r0], r1 ;load src data
72 vld1.u8 {q4}, [r0], r1
74 vld1.u8 {q5}, [r0], r1
76 vld1.u8 {q6}, [r0], r1
145 vld1.u8 {q3}, [r0], r1 ;load src data
153 vld1.u8 {q4}, [r0], r1
155 vld1.u8 {q5}, [r0], r1
157 vld1.u8 {q6}, [r0], r1
163 ;vld1.u8 {q3}, [r0], r1 ;load src dat
[all...] |
| shortidct4x4llm_neon.asm | 41 vld1.16 {q1, q2}, [r0]
42 vld1.16 {d0}, [r12]
110 vld1.32 d6[0], [r1], r2
111 vld1.32 d6[1], [r1], r2
112 vld1.32 d7[0], [r1], r2
113 vld1.32 d7[1], [r1], r2
|
| idct_dequant_full_2x_neon.asm | 25 vld1.16 {q0, q1}, [r1] ; dq (same l/r)
26 vld1.16 {q2, q3}, [r0] ; l q
28 vld1.16 {q4, q5}, [r0] ; r q
32 vld1.32 {d28[0]}, [r2], r3 ; l pre
33 vld1.32 {d28[1]}, [r12], r3 ; r pre
34 vld1.32 {d29[0]}, [r2], r3
35 vld1.32 {d29[1]}, [r12], r3
36 vld1.32 {d30[0]}, [r2], r3
37 vld1.32 {d30[1]}, [r12], r3
38 vld1.32 {d31[0]}, [r2], r
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| loopfilter_mb_neon.asm | 34 vld1.8 {d16[]}, [r2] ; load *blimit
35 vld1.8 {d17[]}, [r3] ; load *limit
36 vld1.8 {d18[]}, [r4] ; load *thresh
40 vld1.u8 {d0}, [r8@64], r1 ; p7
41 vld1.u8 {d1}, [r8@64], r1 ; p6
42 vld1.u8 {d2}, [r8@64], r1 ; p5
43 vld1.u8 {d3}, [r8@64], r1 ; p4
44 vld1.u8 {d4}, [r8@64], r1 ; p3
45 vld1.u8 {d5}, [r8@64], r1 ; p2
46 vld1.u8 {d6}, [r8@64], r1 ; p
[all...] |
| idct8x8_add_neon.asm | 210 vld1.s16 {q8,q9}, [r0]!
211 vld1.s16 {q10,q11}, [r0]!
212 vld1.s16 {q12,q13}, [r0]!
213 vld1.s16 {q14,q15}, [r0]!
269 vld1.64 {d0}, [r1], r2
270 vld1.64 {d1}, [r1], r2
271 vld1.64 {d2}, [r1], r2
272 vld1.64 {d3}, [r1], r2
273 vld1.64 {d4}, [r1], r2
274 vld1.64 {d5}, [r1], r
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_mb_lpf_neon.asm | 34 vld1.8 {d16[]}, [r2] ; load *blimit
35 vld1.8 {d17[]}, [r3] ; load *limit
36 vld1.8 {d18[]}, [r4] ; load *thresh
40 vld1.u8 {d0}, [r8@64], r1 ; p7
41 vld1.u8 {d1}, [r8@64], r1 ; p6
42 vld1.u8 {d2}, [r8@64], r1 ; p5
43 vld1.u8 {d3}, [r8@64], r1 ; p4
44 vld1.u8 {d4}, [r8@64], r1 ; p3
45 vld1.u8 {d5}, [r8@64], r1 ; p2
46 vld1.u8 {d6}, [r8@64], r1 ; p
[all...] |
| vp9_idct8x8_add_neon.asm | 210 vld1.s16 {q8,q9}, [r0]!
211 vld1.s16 {q10,q11}, [r0]!
212 vld1.s16 {q12,q13}, [r0]!
213 vld1.s16 {q14,q15}, [r0]!
269 vld1.64 {d0}, [r1], r2
270 vld1.64 {d1}, [r1], r2
271 vld1.64 {d2}, [r1], r2
272 vld1.64 {d3}, [r1], r2
273 vld1.64 {d4}, [r1], r2
274 vld1.64 {d5}, [r1], r
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/ |
| h264bsdFillRow7.S | 77 VLD1.8 {qTmp0, qTmp1}, [ref]!
83 VLD1.8 {dTmp0,dTmp1,dTmp2}, [ref]!
90 VLD1.8 {dTmp0,dTmp1,dTmp2}, [ref]!
95 VLD1.8 {qTmp0}, [ref]!
102 VLD1.8 {qTmp0}, [ref]!
107 VLD1.8 {dTmp0}, [ref]!
|
| /external/clang/test/CodeGen/ |
| arm-neon-misc.c | 17 // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8
27 // CHECK: call <2 x i64> @llvm.arm.neon.vld1.v2i64.p0i8
30 // CHECK: call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8
|
| /external/boringssl/linux-arm/crypto/aes/ |
| bsaes-armv7.S | 20 @ it can be compiled for either endianness] by courtesy of vld1.8's
1012 vld1.8 {q7}, [r4]! @ load round 0 key
1018 vld1.8 {q15}, [r4]! @ load round 1 key
1051 vld1.8 {q15}, [r4]! @ load next round key
1132 vld1.8 {q15}, [r8] @ load IV
1140 vld1.8 {q0,q1}, [r0]! @ load input
1141 vld1.8 {q2,q3}, [r0]!
1147 vld1.8 {q4,q5}, [r0]!
1149 vld1.8 {q6,q7}, [r0]
1156 vld1.8 {q8,q9}, [r0]! @ reload inpu
[all...] |
| /external/llvm/test/Analysis/TypeBasedAliasAnalysis/ |
| intrinsics.ll | 10 ; CHECK-NEXT: %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) [[NUW:#[0-9]+]]
15 %a = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind, !tbaa !2
17 %b = call <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8* %p, i32 16) nounwind, !tbaa !2
22 declare <8 x i16> @llvm.arm.neon.vld1.v8i16.p0i8(i8*, i32) nounwind readonly
|
