| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.s | 103 VLD1 qSrcA01, [pSrc], srcStep ;// Load A register [a0 a1 a2 a3 ..]
107 ; VLD1 qSrcB01, [pSrc], srcStep ;// Load B register [a0 a1 a2 a3 ..]
115 VLD1 qSrcB01, [pSrc], srcStep ;// Load B register [a0 a1 a2 a3 ..]
116 ; VLD1 qSrcC01, [pSrc], srcStep ;// Load C register [a0 a1 a2 a3 ..]
133 VLD1 qSrcC01, [pSrc], srcStep ;// Load C register [a0 a1 a2 a3 ..]
134 ; VLD1 qSrcD01, [pSrc], srcStep ;// Load D register [a0 a1 a2 a3 ..]
152 VLD1 qSrcD01, [pSrc], srcStep ;// Load D register [a0 a1 a2 a3 ..]
|
| /external/libavc/common/arm/ |
| ih264_inter_pred_chroma_a9q.s | 143 vld1.8 {d0, d1, d2}, [r0], r2 @ Load row0
144 vld1.8 {d5, d6, d7}, [r0], r2 @ Load row1
167 vld1.8 {d5, d6, d7}, [r0], r2 @ Load row1
195 vld1.8 {d0, d1}, [r0], r2 @ Load row0
196 vld1.8 {d2, d3}, [r0], r2 @ Load row1
210 vld1.8 {d2, d3}, [r0], r2 @ Load row1
228 vld1.8 {d0}, [r0], r2 @ Load row0
230 vld1.8 {d2}, [r0], r2 @ Load row1
236 vld1.8 {d6}, [r0] @ Load row2
|
| ih264_iquant_itrans_recon_dc_a9.s | 147 vld1.32 d30[0], [r1], r3 @I row Load pu1_pred buffer
149 vld1.32 d30[1], [r1], r3 @II row Load pu1_pred buffer
151 vld1.32 d31[0], [r1], r3 @III row Load pu1_pred buf
153 vld1.32 d31[1], [r1], r3 @IV row Load pu1_pred buffer
261 vld1.32 d24, [r1], r3 @ Q12 = 0x070605....0x070605....
263 vld1.32 d25, [r1], r3 @ Q12 = 0x070605....0x070605....
265 vld1.32 d26, [r1], r3 @ Q12 = 0x070605....0x070605....
267 vld1.32 d27, [r1], r3 @ Q12 = 0x070605....0x070605....
269 vld1.32 d28, [r1], r3 @ Q12 = 0x070605....0x070605....
271 vld1.32 d29, [r1], r3 @ Q12 = 0x070605....0x070605...
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_itrans_recon_4x4.s | 140 vld1.16 d4,[r8] @loading first row of g_ai2_ihevc_trans_4_transpose
145 vld1.16 d1,[r9] @loading pi2_src 2nd row
146 vld1.16 d3,[r10] @loading pi2_src 4th row
147 vld1.16 d0,[r0],r4 @loading pi2_src 1st row
148 vld1.16 d2,[r0],r4 @loading pi2_src 3rd row
155 vld1.32 d22[0], [r2],r5
182 vld1.32 d22[1], [r2],r5
186 vld1.32 d23[0], [r2],r5
203 vld1.32 d23[1], [r2],r5
|
| ihevc_sao_edge_offset_class1_chroma.s | 115 VLD1.8 D6,[r14] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
116 VLD1.8 D7,[r6] @offset_tbl_u = vld1_s8(pi1_sao_offset_u)
117 VLD1.8 D8,[r7] @offset_tbl_v = vld1_s8(pi1_sao_offset_v)
130 VLD1.8 D28,[r11]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd)
131 VLD1.8 D29,[r11]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd)
132 VLD1.8 D10,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
133 VLD1.8 D11,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
135 VLD1.8 D30,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
136 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
147 VLD1.8 D18,[r10]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd
[all...] |
| ihevc_deblk_chroma_horz.s | 60 vld1.8 {d0},[r0]
66 vld1.8 {d2},[r12]
69 vld1.8 {d4},[r5]
71 vld1.8 {d16},[r6]
|
| ihevc_sao_edge_offset_class1.s | 111 VLD1.8 D6,[r14] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
112 VLD1.8 D7,[r6] @offset_tbl = vld1_s8(pi1_sao_offset)
125 VLD1.8 D8,[r9]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd)
126 VLD1.8 D9,[r9]! @pu1_top_row = vld1q_u8(pu1_src_top_cpy || pu1_src - src_strd)
127 VLD1.8 D10,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
128 VLD1.8 D11,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
130 VLD1.8 D30,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
131 VLD1.8 D31,[r12]! @vld1q_u8(pu1_src[(ht - 1) * src_strd])
142 VLD1.8 D18,[r10]! @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
143 VLD1.8 D19,[r10] @pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| vbsl-constant.ll | 62 ;CHECK: vld1.32
63 ;CHECK: vld1.32
76 ;CHECK: vld1.32
77 ;CHECK: vld1.32
90 ;CHECK: vld1.32
91 ;CHECK: vld1.32
104 ;CHECK: vld1.32
105 ;CHECK: vld1.32
106 ;CHECK: vld1.64
|
| nop_concat_vectors.ll | 4 ;CHECK-NOT: vld1.32
|
| unaligned_load_store.ll | 39 ; EXPANDED-NOT: vld1
45 ; UNALIGNED: vld1.16
55 ; EXPANDED-NOT: vld1
61 ; UNALIGNED: vld1.8
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.S | 31 VLD1.8 {d0,d1},[r0],r1
42 VLD1.8 {d0,d1},[r0],r1
53 VLD1.8 {d0,d1},[r0],r1
65 VLD1.8 {d0,d1},[r0],r1
77 VLD1.8 {d0,d1},[r0],r1
89 VLD1.8 {d0,d1},[r0],r1
101 VLD1.8 {d0,d1},[r0],r1
113 VLD1.8 {d0,d1},[r0],r1
125 VLD1.8 {d0,d1},[r0],r1
|
| armVCM4P10_InterpolateLuma_HalfHor4x4_unsafe_s.S | 31 VLD1.8 {d22,d23},[r0],r1
40 VLD1.8 {d24,d25},[r0],r1
52 VLD1.8 {d26,d27},[r0],r1
64 VLD1.8 {d28,d29},[r0],r1
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Norm_Corr_neon.s | 73 VLD1.S16 {Q0, Q1}, [r14]!
74 VLD1.S16 {Q2, Q3}, [r14]!
75 VLD1.S16 {Q4, Q5}, [r14]!
76 VLD1.S16 {Q6, Q7}, [r14]!
116 VLD1.S16 {Q0, Q1}, [r14]! @ load 16 excf[]
117 VLD1.S16 {Q2, Q3}, [r14]! @ load 16 excf[]
118 VLD1.S16 {Q4, Q5}, [r12]! @ load 16 x[]
119 VLD1.S16 {Q6, Q7}, [r12]! @ load 16 x[]
137 VLD1.S16 {Q0, Q1}, [r14]! @ load 16 excf[]
138 VLD1.S16 {Q2, Q3}, [r14]! @ load 16 excf[
[all...] |
| pred_lt4_1_neon.s | 51 VLD1.S16 {Q0, Q1}, [r11]!
52 VLD1.S16 {Q2, Q3}, [r11]!
56 VLD1.S16 {Q4, Q5}, [r4]! @load 16 x[]
57 VLD1.S16 {Q6, Q7}, [r4]! @load 16 x[]
|
| syn_filt_neon.s | 45 VLD1.S16 {D0, D1, D2, D3}, [r4]! @load 16 mems
53 VLD1.S16 {D0, D1, D2, D3}, [r0]! @ load a[1] ~ a[16]
62 VLD1.S16 {D4, D5, D6, D7}, [r10]! @ first 16 temp_p
96 VLD1.S16 {D0, D1, D2, D3}, [r5]!
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| sixtappredict8x4_neon.asm | 50 vld1.s32 {q14, q15}, [r2] ;load first_pass filter
67 vld1.u8 {q3}, [r0], r1 ;load src data
69 vld1.u8 {q4}, [r0], r1
71 vld1.u8 {q5}, [r0], r1
73 vld1.u8 {q6}, [r0], r1
139 vld1.u8 {q3}, [r0], r1 ;load src data
146 vld1.u8 {q4}, [r0], r1
148 vld1.u8 {q5}, [r0], r1
150 vld1.u8 {q6}, [r0], r1
152 vld1.u8 {q7}, [r0], r
[all...] |
| sixtappredict16x16_neon.asm | 58 vld1.s32 {q14, q15}, [r2] ;load first_pass filter
81 vld1.u8 {d6, d7, d8}, [r0], r1 ;load src data
82 vld1.u8 {d9, d10, d11}, [r0], r1
83 vld1.u8 {d12, d13, d14}, [r0], r1
203 vld1.s32 {q5, q6}, [r3] ;load second_pass filter
219 vld1.u8 {d18}, [lr], r2 ;load src data
220 vld1.u8 {d19}, [lr], r2
221 vld1.u8 {d20}, [lr], r2
222 vld1.u8 {d21}, [lr], r2
224 vld1.u8 {d22}, [lr], r
[all...] |
| loopfiltersimplehorizontaledge_neon.asm | 28 vld1.u8 {q7}, [r0@128], r1 ; q0
29 vld1.u8 {q5}, [r3@128], r1 ; p0
30 vld1.u8 {q8}, [r0@128] ; q1
31 vld1.u8 {q6}, [r3@128] ; p1
|
| /external/libjpeg-turbo/simd/ |
| jsimd_arm_neon.S | 243 vld1.16 {d16, d17, d18, d19}, [COEF_BLOCK, :128]!
244 vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
245 vld1.16 {d20, d21, d22, d23}, [COEF_BLOCK, :128]!
247 vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
249 vld1.16 {d24, d25, d26, d27}, [COEF_BLOCK, :128]!
251 vld1.16 {d0, d1, d2, d3}, [DCT_TABLE, :128]!
253 vld1.16 {d28, d29, d30, d31}, [COEF_BLOCK, :128]
255 vld1.16 {d4, d5, d6, d7}, [DCT_TABLE, :128]!
258 vld1.16 {d0, d1, d2, d3}, [ip, :128] /* load constants */
337 vld1.s16 {d2}, [ip, :64] /* reload constants *
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| intrapred_neon_asm.asm | 38 vld1.32 {d0[0]}, [r2]
55 vld1.8 {d0}, [r2]
76 vld1.8 {q0}, [r2]
105 vld1.8 {q0, q1}, [r2]
138 vld1.32 {d1[0]}, [r3]
159 vld1.64 {d1}, [r3]
188 vld1.8 {q1}, [r3]
236 vld1.8 {q1}, [r3]!
301 vld1.u8 {d0[]}, [r12]
304 vld1.32 {d2[0]}, [r2
[all...] |
| /external/boringssl/src/crypto/aes/asm/ |
| bsaes-armv7.pl | 20 # it can be compiled for either endianness] by courtesy of vld1.8's
947 vld1.8 {@XMM[7]}, [$inp]! @ load round 0 key
953 vld1.8 {@XMM[15]}, [$inp]! @ load round 1 key
986 vld1.8 {@XMM[15]}, [$inp]! @ load next round key
1035 vld1.8 {@XMM[0]-@XMM[1]}, [$inp]! @ load input
1036 vld1.8 {@XMM[2]-@XMM[3]}, [$inp]!
1038 vld1.8 {@XMM[4]-@XMM[5]}, [$inp]!
1040 vld1.8 {@XMM[6]-@XMM[7]}, [$inp]!
1087 vld1.8 {@XMM[0]-@XMM[1]}, [$inp]! @ load input
1088 vld1.8 {@XMM[2]-@XMM[3]}, [$inp]
[all...] |
| /external/libmpeg2/common/arm/ |
| icv_variance_a9.s | 74 vld1.8 d0, [r0], r1
75 vld1.8 d1, [r0], r1
76 vld1.8 d2, [r0], r1
77 vld1.8 d3, [r0], r1
|
| /external/llvm/test/CodeGen/Thumb2/ |
| buildvector-crash.ll | 16 ; CHECK: vld1.64
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Convolve.S | 36 vld1.16 {q0, q1}, [r4]
46 vld1.8 {q13}, [r1], r5
47 vld1.8 {q14}, [r2], r5
48 vld1.8 {q15}, [r3], r5
132 vld1.16 {d0, d1, d2, d3}, [r6]!
133 vld1.16 {d4, d5, d6}, [r6]
145 vld1.8 {d24, d25, d26}, [r1], r7 @ y0 ( y - 2 )
146 vld1.8 {d27, d28, d29}, [r2], r7 @ y0 ( y - 1 )
191 vld1.8 {d24, d25, d26}, [r3], r7 @ y0 ( y )
192 vld1.8 {d27, d28, d29}, [r4], r7 @ y0 ( y + 1
[all...] |
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| memcpy_base.S | 72 vld1.32 {d0[0]}, [r1]!
76 vld1.8 {d0}, [r1]!
92 vld1.8 {d0 - d3}, [r1]!
93 vld1.8 {d4 - d7}, [r1]!
106 vld1.8 {d0 - d3}, [r1]!
116 vld1.8 {d0, d1}, [r1]!
121 vld1.8 {d0}, [r1]!
124 vld1.32 {d0[0]}, [r1]!
|
