| /external/boringssl/src/crypto/bn/asm/ |
| armv4-mont.pl | 291 vld1.32 {${Bi}[0]}, [$bptr,:32]!
293 vld1.32 {$A0-$A3}, [$aptr]! @ can't specify :32 :-(
295 vld1.32 {${M0}[0]}, [$n0,:32]
312 vld1.32 {$N0-$N3}, [$nptr]!
349 vld1.32 {${Bi}[0]}, [$bptr,:32]!
409 vld1.32 {$A0-$A3}, [$aptr]!
416 vld1.32 {$N0-$N1}, [$nptr]!
424 vld1.32 {$N2-$N3}, [$nptr]!
443 vld1.64 {$Temp}, [sp,:128]
451 vld1.64 {$A0xB}, [$tinptr, :128]
[all...] |
| /external/clang/test/CodeGen/ |
| asm_arm.c | 28 // CHECK: call void asm sideeffect "vld1.32 {d8[],d9[]},
30 "vld1.32 {d8[],d9[]}, [%1,:32] \n\t"
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| compare_neon.cc | 33 "vld1.8 {q0}, [%0]! \n"
35 "vld1.8 {q1}, [%1]! \n"
|
| scale_neon.cc | 53 "vld1.8 {q0, q1}, [%0]! \n" // load pixels and post inc
79 "vld1.8 {q0, q1}, [%0]! \n" // load row 1 and post inc
81 "vld1.8 {q2, q3}, [%1]! \n" // load row 2 and post inc
129 "vld1.8 {q0}, [%0]! \n" // load up 16x4
131 "vld1.8 {q1}, [%3]! \n"
133 "vld1.8 {q2}, [%4]! \n"
135 "vld1.8 {q3}, [%5]! \n"
302 "vld1.8 {q3}, [%3] \n"
306 "vld1.8 {d0, d1, d2, d3}, [%0]! \n"
331 "vld1.16 {q13}, [%5] \n
[all...] |
| /external/libyuv/files/source/ |
| compare_neon.cc | 34 "vld1.8 {q0}, [%0]! \n"
36 "vld1.8 {q1}, [%1]! \n"
|
| scale_neon.cc | 51 "vld1.8 {q0, q1}, [%0]! \n" // load pixels and post inc
76 "vld1.8 {q0, q1}, [%0]! \n" // load row 1 and post inc
78 "vld1.8 {q2, q3}, [%1]! \n" // load row 2 and post inc
124 "vld1.8 {q0}, [%0]! \n" // load up 16x4
126 "vld1.8 {q1}, [%3]! \n"
128 "vld1.8 {q2}, [%4]! \n"
130 "vld1.8 {q3}, [%5]! \n"
294 "vld1.8 {q3}, [%3] \n"
297 "vld1.8 {d0, d1, d2, d3}, [%0]! \n"
322 "vld1.16 {q13}, [%5] \n
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| memcpy-inline.ll | 33 ; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
37 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
49 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
51 ; CHECK: vld1.64 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]
60 ; CHECK: vld1.8 {d{{[0-9]+}}, d{{[0-9]+}}}, [r1]!
71 ; CHECK: vld1.64 {[[REG3:d[0-9]+]], [[REG4:d[0-9]+]]}, [r1]
104 ; CHECK: vld1.16
120 ; CHECK: vld1.32
|
| no-fpu.ll | 10 ; NONEON-NOVFP-NOT: vld1.64
11 ; NONEON-NOT: vld1.64
|
| 2012-08-09-neon-extload.ll | 21 ; CHECK: vld1.16 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:16]
35 ; CHECK: vld1.16 {d{{[0-9]+}}[0]}, [{{r[0-9]+}}:16]
53 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
68 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
82 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
97 ; CHECK: vld1.32 {d[[LOAD:[0-9]+]][0]}, [{{r[0-9]+}}:32]
|
| unaligned_load_store_vector.ll | 13 ;CHECK: vld1.8
31 ;CHECK: vld1.8
49 ;CHECK: vld1.8
67 ;CHECK: vld1.8
85 ;CHECK: vld1.8
103 ;CHECK: vld1.8
121 ;CHECK: vld1.8
139 ;CHECK: vld1.8
157 ;CHECK: vld1.8
175 ;CHECK: vld1.1
[all...] |
| /bionic/libc/arch-arm/cortex-a53/bionic/ |
| memcpy_base.S | 91 vld1.8 {d0}, [r1]!
99 vld1.8 {d0 - d3}, [r1]!
100 vld1.8 {d4 - d7}, [r1]!
111 vld1.8 {d0 - d3}, [r1]!
119 vld1.8 {d0, d1}, [r1]!
126 vld1.8 {d0}, [r1]!
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm/ |
| h264bsdFillRow7.s | 118 VLD1 {qTmp0, qTmp1}, [ref]!
124 VLD1 {dTmp0,dTmp1,dTmp2}, [ref]!
131 VLD1 {dTmp0,dTmp1,dTmp2}, [ref]!
136 VLD1 qTmp0, [ref]!
143 VLD1 qTmp0, [ref]!
148 VLD1 dTmp0, [ref]!
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Blur.S | 86 vld1.8 {d30,d31}, [r1]
121 vld1.8 {d20,d21}, [r10], r2
122 vld1.8 {d22,d23}, [r11]
145 vld1.8 {d20,d21}, [r10]
146 vld1.8 {d22,d23}, [r11]
743 vld1.u16 {d24,d25}, [r12:128]
750 vld1.u16 {d24}, [r12:64]!
752 vld1.u16 {d25}, [r12:64]
759 vld1.u16 {d24,d25}, [r12:128]
766 vld1.u16 {d24}, [r12:64]
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| idct16x16_add_neon.asm | 611 vld1.s16 {q0}, [r2], r4 ; load data step2[0]
612 vld1.s16 {q1}, [r2], r4 ; load data step2[1]
613 vld1.s16 {q10}, [r2], r4 ; load data step2[2]
614 vld1.s16 {q11}, [r2], r4 ; load data step2[3]
615 vld1.64 {d12}, [r7], r8 ; load destinatoin data
616 vld1.64 {d13}, [r7], r8 ; load destinatoin data
629 vld1.64 {d12}, [r7], r8 ; load destinatoin data
630 vld1.64 {d13}, [r7], r8 ; load destinatoin data
643 vld1.s16 {q0}, [r2], r4 ; load data step2[4]
644 vld1.s16 {q1}, [r2], r4 ; load data step2[5
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_idct16x16_add_neon.asm | 611 vld1.s16 {q0}, [r2], r4 ; load data step2[0]
612 vld1.s16 {q1}, [r2], r4 ; load data step2[1]
613 vld1.s16 {q10}, [r2], r4 ; load data step2[2]
614 vld1.s16 {q11}, [r2], r4 ; load data step2[3]
615 vld1.64 {d12}, [r7], r8 ; load destinatoin data
616 vld1.64 {d13}, [r7], r8 ; load destinatoin data
629 vld1.64 {d12}, [r7], r8 ; load destinatoin data
630 vld1.64 {d13}, [r7], r8 ; load destinatoin data
643 vld1.s16 {q0}, [r2], r4 ; load data step2[4]
644 vld1.s16 {q1}, [r2], r4 ; load data step2[5
[all...] |
| /external/boringssl/linux-arm/crypto/modes/ |
| ghashv8-armx32.S | 11 vld1.64 {q9},[r1] @ load input H
61 vld1.64 {q9},[r0] @ load Xi
63 vld1.64 {q12,q13},[r1] @ load twisted H, ...
103 vld1.64 {q0},[r0] @ load [rotated] Xi
119 vld1.64 {q12,q13},[r1]! @ load twisted H, ..., H^2
121 vld1.64 {q14},[r1]
124 vld1.64 {q8},[r2]! @ load [rotated] I[0]
132 vld1.64 {q9},[r2],r12 @ load [rotated] I[1]
155 vld1.64 {q8},[r2],r12 @ load [rotated] I[i+2]
164 vld1.64 {q9},[r2],r12 @ load [rotated] I[i+3
[all...] |
| /external/libavc/common/arm/ |
| ih264_iquant_itrans_recon_a9.s | 167 vld1.32 d30[0], [r1], r3 @I row Load pu1_pred buffer
177 vld1.32 d30[1], [r1], r3 @II row Load pu1_pred buffer
184 vld1.32 d31[0], [r1], r3 @III row Load pu1_pred buf
203 vld1.32 d31[1], [r1], r3 @IV row Load pu1_pred buffer
393 vld1.u8 d0, [r2], r4 @Loading out buffer 16 coeffs
394 vld1.u8 d1, [r2], r4
395 vld1.u8 d2, [r2], r4
396 vld1.u8 d3, [r2], r4
501 vld1.32 {q13}, [r5]! @ Q13 = dequant values row 0
502 vld1.32 {q10}, [r6]! @ Q10 = scaling factors row
[all...] |
| ih264_weighted_bi_pred_a9q.s | 169 vld1.32 d4[0], [r0], r3 @load row 1 in source 1
170 vld1.32 d4[1], [r0], r3 @load row 2 in source 1
171 vld1.32 d6[0], [r1], r4 @load row 1 in source 2
172 vld1.32 d6[1], [r1], r4 @load row 2 in source 2
175 vld1.32 d8[0], [r0], r3 @load row 3 in source 1
176 vld1.32 d8[1], [r0], r3 @load row 4 in source 1
178 vld1.32 d10[0], [r1], r4 @load row 3 in source 2
179 vld1.32 d10[1], [r1], r4 @load row 4 in source 2
210 vld1.8 d4, [r0], r3 @load row 1 in source 1
211 vld1.8 d6, [r1], r4 @load row 1 in source
[all...] |
| ih264_intra_pred_luma_8x8_a9q.s | 108 vld1.u8 {q0}, [r0]! @
109 vld1.u8 {q1}, [r0]
115 vld1.8 {d10[7]}, [r0] @ LOADING SRC[24] AGIN TO THE END FOR p'[ 15, -1 ] = ( p[ 14, -1 ] + 3 * p[ 15, -1 ] + 2 ) >> 2
199 vld1.8 d0, [r0]
271 vld1.u8 {d0}, [r0]
357 vld1.u8 {d0}, [r0] @BOTH LEFT AND TOP AVAILABLE
359 vld1.u8 {d1}, [r0]
373 vld1.u8 {d0}, [r0]
382 vld1.u8 {d0}, [r0]
464 vld1.8 {q0}, [r0
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_chroma_horz.s | 119 vld1.16 {q0},[r12] @load 16 values. d1[7] will have the 1st value.
121 vld1.16 {q5},[r12] @load 16 values. d1[7] will have the 1st value.
195 @vld1.8 {q15},[r12] @pu1_ref[two_nt + 1 + col]
199 vld1.8 {q0},[r12]
202 vld1.8 {q15},[r12]
274 @vld1.8 {d30},[r12] @pu1_ref[two_nt + 1 + col]
277 vld1.8 {d0},[r12]
279 vld1.8 {d30},[r12]
318 vld1.8 {d30},[r12] @pu1_ref[two_nt + 1 + col]
321 vld1.8 {d0},[r12
[all...] |
| ihevc_intra_pred_luma_dc.s | 149 vld1.s8 d0, [r6]! @load from src[nt]
151 vld1.s8 d1, [r8]! @load from src[2nt+1]
158 vld1.s8 d0, [r6]! @load from src[nt] (extra load for 8)
160 vld1.s8 d1, [r8]! @load from src[2nt+1] (extra load for 8)
180 vld1.s8 d0, [r6]! @load from src[nt] (extra load for 16)
183 vld1.s8 d1, [r8]! @load from src[2nt+1] (extra load for 16)
223 vld1.s8 d0, [r8]! @col 1::7 load (prol)
226 vld1.s8 d1, [r9] @row 7::1 (0 also) load (prol)
231 vld1.s8 d6, [r8] @col 8::15 load (prol extra)
295 vld1.s8 d1, [r9] @row 8::15 load (prol extra
[all...] |
| /external/boringssl/src/crypto/poly1305/ |
| poly1305_arm_asm.S | 173 # asm 1: vld1.8 {<y0=reg128#1%bot},[<input_1=int32#2]!
174 # asm 2: vld1.8 {<y0=d0},[<input_1=r1]!
175 vld1.8 {d0},[r1]!
178 # asm 1: vld1.8 {>y12=reg128#2%bot->y12=reg128#2%top},[<input_1=int32#2]!
179 # asm 2: vld1.8 {>y12=d2->y12=d3},[<input_1=r1]!
180 vld1.8 {d2-d3},[r1]!
183 # asm 1: vld1.8 {>y34=reg128#3%bot->y34=reg128#3%top},[<input_1=int32#2]!
184 # asm 2: vld1.8 {>y34=d4->y34=d5},[<input_1=r1]!
185 vld1.8 {d4-d5},[r1]!
195 # asm 1: vld1.8 {<z0=reg128#4%bot},[<input_1=int32#2]
[all...] |
| /external/llvm/test/Transforms/LoopStrengthReduce/ARM/ |
| ivchain-ARM.ll | 242 %12 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %.05, i32 1) nounwind
244 %14 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %13, i32 1) nounwind
250 %19 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %18, i32 1) nounwind
252 %21 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %20, i32 1) nounwind
258 %26 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %25, i32 1) nounwind
260 %28 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %27, i32 1) nounwind
266 %33 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %32, i32 1) nounwind
268 %35 = tail call <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8* %34, i32 1) nounwind
293 declare <1 x i64> @llvm.arm.neon.vld1.v1i64.p0i8(i8*, i32) nounwind readonly
301 ; A9: vld1.8 {d{{[0-9]+}}}, [[BASE:[r[0-9]+]]], [[INC:r[0-9]]
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfDiagHorVer4x4_unsafe_s.s | 111 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
124 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
138 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
155 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
172 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
189 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
206 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
223 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
240 VLD1 qSrc01, [pSrc], srcStep ;// [a0 a1 a2 a3 ..]
|
| /frameworks/av/services/audioflinger/ |
| AudioResamplerFirProcessNeon.h | 55 "vld1.s32 {d2}, [%[vLR]:64] \n"/* (1) load volumes */\
56 "vld1.s32 {d3}, %[out] \n"/* (2) unaligned load the output */\
64 "vld1.s32 {d2}, [%[vLR]:64] \n"/* (1) load volumes*/\
65 "vld1.s32 {d3}, %[out] \n"/* (2) unaligned load the output*/\
546 "vld1.16 {q2}, [%[sP]] \n"// (2+0d) load 8 16-bits mono samples
547 "vld1.16 {q3}, [%[sN]]! \n"// (2) load 8 16-bits mono samples
548 "vld1.16 {q8}, [%[coefsP0]:128]! \n"// (1) load 8 16-bits coefs
549 "vld1.16 {q10}, [%[coefsN0]:128]! \n"// (1) load 8 16-bits coefs
606 "vld1.16 {q8}, [%[coefsP0]:128]! \n"// (1) load 8 16-bits coefs
607 "vld1.16 {q10}, [%[coefsN0]:128]! \n"// (1) load 8 16-bits coef
[all...] |
