| /external/libavc/common/arm/ |
| ih264_weighted_pred_a9q.s | 136 vld1.32 d4[0], [r0], r2 @load row 1 in source
137 vld1.32 d4[1], [r0], r2 @load row 2 in source
138 vld1.32 d6[0], [r0], r2 @load row 3 in source
139 vld1.32 d6[1], [r0], r2 @load row 4 in source
168 vld1.8 d4, [r0], r2 @load row 1 in source
169 vld1.8 d6, [r0], r2 @load row 2 in source
170 vld1.8 d8, [r0], r2 @load row 3 in source
172 vld1.8 d10, [r0], r2 @load row 4 in source
208 vld1.8 {q2}, [r0], r2 @load row 1 in source
209 vld1.8 {q3}, [r0], r2 @load row 2 in sourc
[all...] |
| ih264_deblk_luma_a9.s | 99 vld1.8 {q5}, [r0], r1 @p2 values are loaded into q5
102 vld1.8 {q4}, [r0], r1 @p1 values are loaded into q4
104 vld1.8 {q3}, [r0], r1 @p0 values are loaded into q3
106 vld1.8 {q0}, [r0], r1 @q0 values are loaded into q0
108 vld1.8 {q1}, [r0], r1 @q1 values are loaded into q1
110 vld1.32 d16[0], [r5] @D16[0] contains cliptab
112 vld1.8 {q2}, [r0], r1 @q2 values are loaded into q2
238 vld1.8 {d4, d5}, [r0], r1 @load q0 to Q2, q0 = q0 + src_strd
239 vld1.8 {d6, d7}, [r12] @load p0 to Q3
240 vld1.8 {d8, d9}, [r0], r1 @load q1 to Q4, q0 = q0 + src_str
[all...] |
| ih264_inter_pred_luma_horz_qpel_a9q.s | 130 vld1.8 {d2, d3, d4}, [r0], r2 @// Load row0
132 vld1.8 {d5, d6, d7}, [r0], r2 @// Load row1
172 vld1.32 {d12, d13}, [r7], r2 @Load value for interpolation (column1,row0)
181 vld1.32 {d12, d13}, [r7], r2 @Load value for interpolation (column1,row1)
192 vld1.8 {d5, d6}, [r0], r2 @// Load row1
194 vld1.8 {d2, d3}, [r0], r2 @// Load row0
215 vld1.32 d12, [r7], r2 @Load value for interpolation (column1,row0)
216 vld1.32 d13, [r7], r2 @Load value for interpolation (column1,row1)
227 vld1.8 {d5, d6}, [r0], r2 @// Load row1
229 vld1.8 {d2, d3}, [r0], r2 @// Load row
[all...] |
| ih264_intra_pred_chroma_a9q.s | 117 vld1.u8 {q0}, [r0] @BOTH LEFT AND TOP AVAILABLE
119 vld1.u8 {q1}, [r0]
145 vld1.u8 {q0}, [r0]
158 vld1.u8 {q0}, [r0]
243 vld1.u8 {q0}, [r0]
320 vld1.8 {q0}, [r0]
390 vld1.32 d0, [r0]
392 vld1.32 d1, [r10]
395 vld1.32 d2, [r10]!
398 vld1.32 d3, [r10
[all...] |
| ih264_inter_pred_luma_horz_hpel_vert_hpel_a9q.s | 136 vld1.u32 {d2, d3, d4}, [r0], r2 @ Vector load from src[0_0]
137 vld1.u32 {d5, d6, d7}, [r0], r2 @ Vector load from src[1_0]
138 vld1.u32 {d8, d9, d10}, [r0], r2 @ Vector load from src[2_0]
139 vld1.u32 {d11, d12, d13}, [r0], r2 @ Vector load from src[3_0]
140 vld1.u32 {d14, d15, d16}, [r0], r2 @ Vector load from src[4_0]
141 vld1.u32 {d17, d18, d19}, [r0], r2 @ Vector load from src[5_0]
198 vld1.u32 {d2, d3, d4}, [r0], r2 @ Vector load from src[6_0]
268 vld1.u32 {d2, d3}, [r0], r2 @ Vector load from src[0_0]
269 vld1.u32 {d4, d5}, [r0], r2 @ Vector load from src[1_0]
270 vld1.u32 {d6, d7}, [r0], r2 @ Vector load from src[2_0
[all...] |
| /external/libvpx/libvpx/vpx_dsp/arm/ |
| idct4x4_add_neon.asm | 36 vld1.s16 {q8,q9}, [r0]!
167 vld1.32 {d26[0]}, [r1], r2
168 vld1.32 {d26[1]}, [r1], r2
169 vld1.32 {d27[1]}, [r1], r2
170 vld1.32 {d27[0]}, [r1] ; no post-increment
|
| /external/llvm/test/CodeGen/ARM/ |
| vuzp.ll | 72 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
73 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
90 ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
91 ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
105 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
106 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
123 ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
124 ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
138 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
139 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0
[all...] |
| vzip.ll | 72 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
73 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
90 ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
91 ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
105 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
106 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
123 ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
124 ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
138 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
139 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0
[all...] |
| inlineasm3.ll | 34 %asmtmp31 = call %0 asm "vld1.u8 {$0}, [$1:128]!\0A", "=w,=r,1"(<16 x i8>* undef) nounwind
120 ; CHECK: vld1.s32 {d16[], d17[]}, [r0]
121 %0 = tail call <4 x i32> asm "vld1.s32 {${0:e}[], ${0:f}[]}, [$1]", "=w,r"(i32* %p) nounwind
|
| 2011-11-29-128bitArithmetics.ll | 11 ; CHECK: vld1.64 {{.*}}, [r1:128]
34 ; CHECK: vld1.64
65 ; CHECK: vld1.64
96 ; CHECK: vld1.64
127 ; CHECK: vld1.64
158 ; CHECK: vld1.64
189 ; CHECK: vld1.64
221 ; CHECK: vld1.64
255 ; CHECK: vld1.64 {{.*}}:128
278 ; CHECK: vld1.6
[all...] |
| /external/llvm/test/CodeGen/Thumb2/ |
| aligned-spill.ll | 39 ; NEON: vld1.64 {d8, d9, d10, d11}, [r[[R4]]:128]!
40 ; NEON: vld1.64 {d12, d13, d14, d15}, [r[[R4]]:128]
64 ; NEON: vld1.64 {d8, d9, d10, d11},
65 ; NEON: vld1.64 {d12, d13},
90 ; NEON: vld1.64 {d8, d9},
|
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| scale_sig_neon.s | 51 VLD1.S16 {Q0, Q1}, [r5]! @load 16 Word16 x[]
67 VLD1.S16 {Q0, Q1}, [r5]! @load 16 Word16 x[]
68 VLD1.S16 {Q2, Q3}, [r5]! @load 16 Word16 x[]
69 VLD1.S16 {Q4, Q5}, [r5]! @load 16 Word16 x[]
70 VLD1.S16 {Q6, Q7}, [r5]! @load 16 Word16 x[]
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_DeblockingChroma_unsafe_s.s | 120 VLD1 d18.U32[0], [pThresholds]! ;here
147 VLD1 {dAlpha[]}, [pAlpha]
150 VLD1 {dBeta[]}, [pBeta]
201 VLD1 {dAlpha[]}, [pAlpha]
203 VLD1 {dBeta[]}, [pBeta]
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_idct4x4_add_neon.asm | 36 vld1.s16 {q8,q9}, [r0]!
167 vld1.32 {d26[0]}, [r1], r2
168 vld1.32 {d26[1]}, [r1], r2
169 vld1.32 {d27[1]}, [r1], r2
170 vld1.32 {d27[0]}, [r1] ; no post-increment
|
| vp9_reconintra_neon.asm | 38 vld1.32 {d0[0]}, [r2]
55 vld1.8 {d0}, [r2]
76 vld1.8 {q0}, [r2]
105 vld1.8 {q0, q1}, [r2]
138 vld1.32 {d1[0]}, [r3]
159 vld1.64 {d1}, [r3]
188 vld1.8 {q1}, [r3]
236 vld1.8 {q1}, [r3]!
305 vld1.32 {d2[0]}, [r2]
352 vld1.8 {d30}, [r3
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_sao_edge_offset_class3_chroma.s | 111 VLD1.8 D0,[r11]! @pu1_src[(ht - 1) * src_strd + col]
278 VLD1.8 D6,[r6] @offset_tbl_u = vld1_s8(pi1_sao_offset_u)
280 VLD1.8 D7,[r6] @offset_tbl_v = vld1_s8(pi1_sao_offset_v)
284 @VLD1.8 D6,[r6] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
314 VLD1.8 D12,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
315 VLD1.8 D13,[r0] @pu1_cur_row = vld1q_u8(pu1_src)
324 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)
325 VLD1.8 D11,[r8] @pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)
355 VLD1.8 D16,[r11]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
356 VLD1.8 D17,[r11] @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd
[all...] |
| ihevc_sao_edge_offset_class2_chroma.s | 113 VLD1.8 D0,[r11]! @pu1_src[(ht - 1) * src_strd + col]
280 VLD1.8 D6,[r6] @offset_tbl_u = vld1_s8(pi1_sao_offset_u)
287 VLD1.8 D7,[r6] @offset_tbl_v = vld1_s8(pi1_sao_offset_v)
319 VLD1.8 D12,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
320 VLD1.8 D13,[r0] @pu1_cur_row = vld1q_u8(pu1_src)
334 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 2) || vld1q_u8(pu1_src_top_cpy - 2)
335 VLD1.8 D11,[r8] @pu1_top_row = vld1q_u8(pu1_src - src_strd - 2) || vld1q_u8(pu1_src_top_cpy - 2)
359 VLD1.8 D16,[r8]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
360 VLD1.8 D17,[r8] @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
401 VLD1.8 D30,[r2] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx
[all...] |
| ihevc_itrans_recon_4x4_ttype1.s | 134 vld1.16 d0,[r0],r4 @loading pi2_src 1st row
136 vld1.16 d1,[r0],r4 @loading pi2_src 2nd row
138 vld1.16 d2,[r0],r4 @loading pi2_src 3rd row
140 vld1.16 d3,[r0],r4 @loading pi2_src 4th row
166 vld1.32 d18[0], [r2],r5
181 vld1.32 d18[1], [r2],r5
195 vld1.32 d19[0], [r2],r5
206 vld1.32 d19[1], [r2],r5
|
| ihevc_weighted_pred_bi.s | 188 vld1.s16 {d0},[r0]! @load and increment the pi2_src1
190 vld1.s16 {d1},[r1]! @load and increment the pi2_src2
192 vld1.s16 {d2},[r6],r3 @load and increment the pi2_src_tmp1 ii iteration
194 vld1.s16 {d3},[r8],r4 @load and increment the pi2_src_tmp1 ii iteration
197 vld1.s16 {d0},[r6],r3 @load and increment the pi2_src1 iii iteration
200 vld1.s16 {d1},[r8],r4 @load and increment the pi2_src2 iii iteration
204 vld1.s16 {d2},[r6],r3 @load and increment the pi2_src_tmp1 iv iteration
208 vld1.s16 {d3},[r8],r4 @load and increment the pi2_src_tmp1 iv iteration
|
| ihevc_sao_band_offset_chroma.s | 98 VLD1.8 D1,[r14]! @band_table_u.val[0]
102 VLD1.8 D2,[r14]! @band_table_u.val[1]
106 VLD1.8 D3,[r14]! @band_table_u.val[2]
114 VLD1.8 D4,[r14]! @band_table_u.val[3]
118 VLD1.8 D0,[r4]! @Load pu1_src[(ht - 1) * src_strd + col]
123 VLD1.8 D30,[r7] @pi1_sao_offset_u load
144 VLD1.8 D9,[r14]! @band_table_v.val[0]
147 VLD1.8 D10,[r14]! @band_table_v.val[1]
203 VLD1.8 D11,[r14]! @band_table_v.val[2]
206 VLD1.8 D12,[r14]! @band_table_v.val[3
[all...] |
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Resize.S | 55 vld1.u8 d16, [r4]!
56 vld1.u8 d18, [r5]!
57 vld1.u8 d20, [r6]!
58 vld1.u8 d22, [r7]!
83 vld1.u32 d16[0], [r4]!
84 vld1.u32 d18[0], [r5]!
85 vld1.u32 d20[0], [r6]!
86 vld1.u32 d22[0], [r7]!
192 vld1.s32 {q4}, [r8]
193 vld1.s16 {q5}, [r9
[all...] |
| /external/llvm/test/MC/Disassembler/ARM/ |
| neon-tests.txt | 12 # CHECK: vld1.8 {d17, d18}, [r6], r5
15 # CHECK: vld1.8 {d17, d18, d19}, [r6], r5
24 # CHECK: vld1.32 {d3[], d4[]}, [r0:32]!
|
| /external/libavc/encoder/arm/ |
| ih264e_evaluate_intra_chroma_modes_a9q.s | 98 vld1.32 {q4}, [r1]!
100 vld1.32 {q5}, [r1]!
158 vld1.32 {q4}, [r12]!
161 vld1.32 {q5}, [r12]!
164 vld1.32 {q0}, [r0], r3
172 vld1.32 {q1}, [r12], r3
199 vld1.32 {q0}, [r0], r3
208 vld1.32 {q1}, [r12], r3
|
| /external/libmpeg2/common/arm/ |
| impeg2_format_conv.s | 143 vld1.8 {q0}, [r0]!
154 @// and written using VLD1 and VST1
159 vld1.8 {q0}, [r0]!
195 vld1.8 d0, [r1]!
196 vld1.8 d1, [r2]!
207 @// and written using VLD1 and VST1
213 vld1.8 d0, [r1]!
214 vld1.8 d1, [r2]!
238 @* VLD1.8 for chroma - order of registers is different *
305 vld1.8 {q0}, [r0]
[all...] |
| /external/clang/test/CodeGen/ |
| arm-vector-align.c | 17 // CHECK: call <4 x float> @llvm.arm.neon.vld1.v4f32.p0i8(i8* %{{.*}}, i32 16)
|
