| /external/libhevc/common/arm/ |
| ihevc_deblk_chroma_vert.s | 63 vld1.8 {d5},[r8],r1
65 vld1.8 {d17},[r8],r1
67 vld1.8 {d16},[r8],r1
69 vld1.8 {d4},[r8]
|
| ihevc_intra_pred_luma_horz.s | 119 vld1.8 {q0},[r12] @load 16 values. d1[7] will have the 1st value.
193 vld1.8 {q15},[r12] @pu1_ref[two_nt + 1 + col]
197 vld1.8 {q0},[r12]
269 vld1.8 {d30},[r12] @pu1_ref[two_nt + 1 + col]
272 vld1.8 {d0},[r12]
311 vld1.8 {d30},[r12] @pu1_ref[two_nt + 1 + col]
314 vld1.8 {d0},[r12]
|
| ihevc_sao_edge_offset_class2.s | 105 VLD1.8 D0,[r11]! @pu1_src[(ht - 1) * src_strd + col]
193 VLD1.8 D7,[r6] @offset_tbl = vld1_s8(pi1_sao_offset)
199 VLD1.8 D6,[r11] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
236 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd - 1) || vld1q_u8(pu1_src_top_cpy - 1)
237 VLD1.8 D11,[r8] @pu1_top_row = vld1q_u8(pu1_src - src_strd - 1) || vld1q_u8(pu1_src_top_cpy - 1)
242 VLD1.8 D12,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
243 VLD1.8 D13,[r0] @pu1_cur_row = vld1q_u8(pu1_src)
269 VLD1.8 D16,[r8]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
270 VLD1.8 D17,[r8] @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
334 VLD1.8 D16,[r8]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd
[all...] |
| ihevc_sao_edge_offset_class3.s | 103 VLD1.8 D0,[r11]! @pu1_src[(ht - 1) * src_strd + col]
205 VLD1.8 D7,[r6] @offset_tbl = vld1_s8(pi1_sao_offset)
215 VLD1.8 D6,[r6] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
251 VLD1.8 D10,[r8]! @pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)
252 VLD1.8 D11,[r8] @pu1_top_row = vld1q_u8(pu1_src - src_strd + 1)
257 VLD1.8 D12,[r0]! @pu1_cur_row = vld1q_u8(pu1_src)
258 VLD1.8 D13,[r0] @pu1_cur_row = vld1q_u8(pu1_src)
280 VLD1.8 D16,[r8]! @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
281 VLD1.8 D17,[r8] @I pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd)
350 VLD1.8 D16,[r8]! @II pu1_next_row = vld1q_u8(pu1_src_cpy + src_strd
[all...] |
| ihevc_sao_edge_offset_class0.s | 96 VLD1.8 D10,[r14] @edge_idx_tbl = vld1_s8(gi1_table_edge_idx)
100 VLD1.8 D11,[r8] @offset_tbl = vld1_s8(pi1_sao_offset)
106 VLD1.8 D0,[r4]! @Load pu1_src[(ht - 1) * src_strd + col]
141 VLD1.8 D12,[r12]! @pu1_cur_row = vld1q_u8(pu1_src_cpy)
142 VLD1.8 D13,[r12], r1 @pu1_cur_row = vld1q_u8(pu1_src_cpy)
150 VLD1.8 D26,[r12]! @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
151 VLD1.8 D27,[r12] @II Iteration pu1_cur_row = vld1q_u8(pu1_src_cpy)
290 VLD1.8 D12,[r12]! @pu1_cur_row = vld1q_u8(pu1_src_cpy)
291 VLD1.8 D13,[r12] @pu1_cur_row = vld1q_u8(pu1_src_cpy)
|
| ihevc_intra_pred_filters_luma_mode_11_to_17.s | 187 vld1.8 d0,[r1]
189 vld1.8 d1,[r1]
191 vld1.8 d2,[r1]
193 vld1.8 d3,[r1]
207 vld1.8 d0,[r1]
209 vld1.8 d1,[r1]
220 vld1.8 d0,[r1]
262 vld1.8 d31, [r14]!
293 vld1.8 {d0,d1}, [r6] @stores the 32 values reqd based on indices values (from least idx)
417 vld1.8 d31, [r14]
[all...] |
| /external/libhevc/decoder/arm/ |
| ihevcd_fmt_conv_420sp_to_420p.s | 118 vld1.8 {d0,d1},[r0]!
127 @// and written using VLD1 and VST1
131 vld1.8 {d0,d1}, [r0]!
181 @// and written using VLD1 and VST1
|
| /external/libopus/celt/arm/ |
| celt_pitch_xcorr_arm.s | 62 VLD1.16 {d5}, [r5]!
79 VLD1.16 {d6, d7}, [r4]!
81 ; assembled to VMOV, like VORR would), so it dual-issues with the prior VLD1.
85 VLD1.16 {d4, d5}, [r5]!
106 VLD1.16 d6, [r4]!
111 VLD1.16 d5, [r5]!
129 VLD1.32 {d5[]}, [r5]!
139 VLD1.16 {d6[]}, [r4]!
146 VLD1.16 {d4[]}, [r5]!
149 VLD1.16 {d6[]}, [r4]
[all...] |
| /external/llvm/test/CodeGen/ARM/ |
| 2009-11-02-NegativeLane.ll | 10 ; CHECK: vld1.16 {d16[], d17[]}
|
| twoaddrinstr.ll | 7 ; CHECK: vld1.32
|
| vtrn.ll | 134 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
135 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
152 ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
153 ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
167 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
168 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0]
185 ; CHECK-NEXT: vld1.64 {d16, d17}, [r2]
186 ; CHECK-NEXT: vld1.64 {d18, d19}, [r1]
200 ; CHECK-NEXT: vld1.64 {d16, d17}, [r1]
201 ; CHECK-NEXT: vld1.64 {d18, d19}, [r0
[all...] |
| vector-DAGCombine.ll | 174 ; Fall back to vld1.32, which can, instead of using the general purpose loads
177 ; CHECK: vld1.32 {[[REG:d[0-9]+]][0]}
178 ; CHECK: vld1.32 {[[REG]][1]}
200 ; CHECK: vld1.32 {{{d[0-9]+}}[0]}, [r0]
214 ; CHECK: vld1.32 {[[REG1:d[0-9]+]][1]}, [r0]
216 ; CHECK: vld1.32 {[[REG1]][0]}, [r1]
217 ; CHECK: vld1.32 {[[REG2]][0]}, [r2]
241 ; CHECK-NEXT: vld1.32 {[[REG1:d[0-9]+]][0]}, {{\[}}[[BASE]]:32]
243 ; CHECK-NEXT: vld1.32 {[[REG1]][1]}, {{\[}}[[BASE2]]:32]
|
| /external/llvm/test/CodeGen/Thumb2/ |
| 2013-03-02-vduplane-nonconstant-source-index.ll | 6 ; CHECK: vld1.32 {[[DREG:d[0-9]+]][], [[DREG2:d[0-9]+]][]}, [r[[SOURCE]]:32]
|
| /external/llvm/test/Transforms/LoopVectorize/ARM/ |
| mul-cast-vect.ll | 20 ; ASM: vld1.64
22 ; ASM: vld1.64
102 ; ASM: vld1.64
104 ; ASM: vld1.64
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Blend.S | 450 vld1.8 {d0-d3}, [r0]!
451 vld1.8 {d4-d7}, [r0]!
460 vld1.8 {d16-d19}, [r1]!
461 vld1.8 {d20-d23}, [r1]!
502 .if \lddst ; vld1.64 {d4-d7}, [r0]! ; .endif
503 .if \ldsrc ; vld1.64 {d20-d23}, [r1]! ; .endif
506 .if \lddst ; vld1.64 {d2-d3}, [r0]! ; .endif
507 .if \ldsrc ; vld1.64 {d18-d19}, [r1]! ; .endif
510 .if \lddst ; vld1.64 {d1}, [r0]! ; .endif
511 .if \ldsrc ; vld1.64 {d17}, [r1]! ; .endi
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/neon/ |
| vp8_shortwalsh4x4_neon.asm | 25 vld1.16 {d0}, [r0@64], r2 ; load input
26 vld1.16 {d1}, [r0@64], r2
27 vld1.16 {d2}, [r0@64], r2
28 vld1.16 {d3}, [r0@64]
|
| /external/boringssl/src/crypto/sha/asm/ |
| sha256-armv4.pl | 488 vld1.8 {@X[0]},[$inp]!
489 vld1.8 {@X[1]},[$inp]!
490 vld1.8 {@X[2]},[$inp]!
491 vld1.8 {@X[3]},[$inp]!
492 vld1.32 {$T0},[$Ktbl,:128]!
493 vld1.32 {$T1},[$Ktbl,:128]!
494 vld1.32 {$T2},[$Ktbl,:128]!
495 vld1.32 {$T3},[$Ktbl,:128]!
540 vld1.8 {@X[0]},[$inp]! @ load next input block
541 vld1.8 {@X[1]},[$inp]
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/common/arm/neon/ |
| vp9_iht4x4_add_neon.asm | 153 vld1.s16 {q8,q9}, [r0]!
214 vld1.32 {d26[0]}, [r1], r2
215 vld1.32 {d26[1]}, [r1], r2
216 vld1.32 {d27[0]}, [r1], r2
217 vld1.32 {d27[1]}, [r1]
|
| /external/libvpx/libvpx/third_party/libyuv/source/ |
| row_neon.cc | 25 "vld1.8 {d0}, [%0]! \n" \
27 "vld1.32 {d2[0]}, [%1]! \n" \
29 "vld1.32 {d2[1]}, [%2]! \n"
34 "vld1.8 {d0}, [%0]! \n" \
36 "vld1.16 {d2[0]}, [%1]! \n" \
38 "vld1.16 {d2[1]}, [%2]! \n" \
45 "vld1.8 {d0}, [%0]! \n" \
47 "vld1.8 {d2}, [%1]! \n" \
49 "vld1.8 {d3}, [%2]! \n" \
56 "vld1.8 {d0}, [%0]! \n"
[all...] |
| /external/libyuv/files/source/ |
| row_neon.cc | 25 "vld1.8 {d0}, [%0]! \n" \
27 "vld1.32 {d2[0]}, [%1]! \n" \
29 "vld1.32 {d2[1]}, [%2]! \n"
34 "vld1.8 {d0}, [%0]! \n" \
36 "vld1.16 {d2[0]}, [%1]! \n" \
38 "vld1.16 {d2[1]}, [%2]! \n" \
45 "vld1.8 {d0}, [%0]! \n" \
47 "vld1.8 {d2}, [%1]! \n" \
49 "vld1.8 {d3}, [%2]! \n" \
56 "vld1.8 {d0}, [%0]! \n"
[all...] |
| /external/gemmlowp/internal/ |
| kernel_neon.h | 113 "vld1.8 {d0}, [%[rhs_ptr]:64]!\n"
116 "vld1.8 {d2}, [%[lhs_ptr]:64]!\n"
117 "vld1.8 {d4}, [%[lhs_ptr]:64]!\n"
118 "vld1.8 {d6}, [%[lhs_ptr]:64]!\n"
179 "vld1.32 {d0, d1}, [r1]!\n"
180 "vld1.32 {d2, d3}, [r1]!\n"
181 "vld1.32 {d4, d5}, [r1]!\n"
190 "vld1.32 {d0, d1}, [r1]!\n"
191 "vld1.32 {d2, d3}, [r1]!\n"
192 "vld1.32 {d4, d5}, [r1]!\n
[all...] |
| /external/libavc/common/arm/ |
| ih264_intra_pred_luma_16x16_a9q.s | 113 vld1.8 {q0}, [r0]
192 vld1.u8 {q0}, [r0]
276 vld1.u8 {q0}, [r0] @BOTH LEFT AND TOP AVAILABLE
279 vld1.u8 {q1}, [r0]
294 vld1.u8 {q0}, [r0]
304 vld1.u8 {q0}, [r0]
401 vld1.32 d2, [r1], r8
406 vld1.32 d0, [r1]
408 vld1.32 {q3}, [r7]
|
| /external/libavc/encoder/arm/ |
| ih264e_fmt_conv.s | 89 vld1.8 {d0, d1}, [r0]!
100 @// and written using VLD1 and VST1
105 vld1.8 {d0, d1}, [r0]!
142 vld1.8 d0, [r1]!
143 vld1.8 d1, [r2]!
154 @// and written using VLD1 and VST1
160 vld1.8 d0, [r1]!
161 vld1.8 d1, [r2]!
313 @// and written using VLD1 and VST1
|
| /external/boringssl/linux-arm/crypto/sha/ |
| sha512-armv4.S | 548 vld1.64 {d0},[r1]! @ handles unaligned
555 vld1.64 {d28},[r3,:64]! @ K[i++]
585 vld1.64 {d1},[r1]! @ handles unaligned
592 vld1.64 {d28},[r3,:64]! @ K[i++]
622 vld1.64 {d2},[r1]! @ handles unaligned
629 vld1.64 {d28},[r3,:64]! @ K[i++]
659 vld1.64 {d3},[r1]! @ handles unaligned
666 vld1.64 {d28},[r3,:64]! @ K[i++]
696 vld1.64 {d4},[r1]! @ handles unaligned
703 vld1.64 {d28},[r3,:64]! @ K[i++
[all...] |
| /external/v8/src/arm/ |
| codegen-arm.cc | 74 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex));
78 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex));
86 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex));
87 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex));
91 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex));
92 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex));
99 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex));
100 __ vld1(Neon8, NeonListOperand(d4, 4), NeonMemOperand(src, PostIndex));
108 __ vld1(Neon8, NeonListOperand(d0, 4), NeonMemOperand(src, PostIndex));
115 __ vld1(Neon8, NeonListOperand(d0, 2), NeonMemOperand(src, PostIndex))
[all...] |
