| /external/v8/src/ |
| d8.js | 9 // Used by the d8 shell to output results.
12 // Hacky solution to circumvent forcing --allow-natives-syntax for d8
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_neon_Convolve.S | 65 d8, d9, d10, d11
72 vmlal.s16 q8, d8, d0[3]
269 vrshrn.i32 d8, q4, #8
274 vqmovun.s16 d8, q4
276 vst1.8 d8, [r0]! @ return the output and increase the address of r0
|
| rsCpuIntrinsics_neon_Blend.S | 93 vrshrn.u16 d8, q0, #8
102 vaddw.u8 q0, d8
139 vrshrn.u16 d8, q0, #8
148 vaddw.u8 q8, d8
183 vrshrn.u16 d8, q0, #8
192 vaddw.u8 q0, d8
222 vrshrn.u16 d8, q0, #8
231 vaddw.u8 q0, d8
370 vrshrn.u16 d8, q0, #8
379 vaddw.u8 q0, d8
[all...] |
| /system/core/debuggerd/arm/ |
| crashglue.S | 27 fconstd d8, #8
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| branch-likely.d | 73 [0-9a-f]+ <[^>]*> beqzl at,0+00d8 <.*\+0xd8>
74 [ ]*d8: .*16 external_label
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mmix/ |
| regt-op.d | 61 d8: 972a0c00 ldunc \$42,\$12,0
125 1d8: b3df1700 stht \$223,\$23,0
|
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-x86-64/ |
| bnd-plt-1.d | 51 [ ]*[a-f0-9]+: e9 d8 ff ff ff jmpq 308 <foo3@plt>
54 [ ]*[a-f0-9]+: e9 d8 ff ff ff jmpq 318 <foo4@plt>
|
| /external/llvm/test/MC/ARM/ |
| eh-directive-section-comdat.s | 24 .vsave {d8, d9, d10, d11, d12}
25 vpush {d8, d9, d10, d11, d12}
30 vpop {d8, d9, d10, d11, d12}
|
| fp-armv8.s | 42 vcvtm.s32.f64 s17, d8
43 @ CHECK: vcvtm.s32.f64 s17, d8 @ encoding: [0xc8,0x8b,0xff,0xfe]
59 vcvtm.u32.f64 s17, d8
60 @ CHECK: vcvtm.u32.f64 s17, d8 @ encoding: [0x48,0x8b,0xff,0xfe]
74 vseleq.f64 d2, d4, d8
75 @ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x08,0x2b,0x04,0xfe]
|
| thumb-fp-armv8.s | 45 vcvtm.s32.f64 s17, d8
46 @ CHECK: vcvtm.s32.f64 s17, d8 @ encoding: [0xff,0xfe,0xc8,0x8b]
62 vcvtm.u32.f64 s17, d8
63 @ CHECK: vcvtm.u32.f64 s17, d8 @ encoding: [0xff,0xfe,0x48,0x8b]
77 vseleq.f64 d2, d4, d8
78 @ CHECK: vseleq.f64 d2, d4, d8 @ encoding: [0x04,0xfe,0x08,0x2b]
|
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/common/arm/neon/ |
| vp8_subpixelvariance8x8_neon.asm | 52 vmull.u8 q9, d8, d0
57 vext.8 d9, d8, d9, #1
79 vmull.u8 q9, d8, d0
85 vext.8 d9, d8, d9, #1
177 vmlal.s16 q9, d8, d8 ;sse
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i860/ |
| bitwise.d | 19 24: 00 d8 9d c3 and %r27,%r28,%r29
30 50: 00 d8 9d d3 andnot %r27,%r28,%r29
41 7c: 00 d8 9d e3 or %r27,%r28,%r29
52 a8: 00 d8 9d f3 xor %r27,%r28,%r29
64 d8: 03 00 e0 c7 and 0x0003,%r31,%r0
128 1d8: 34 12 3a f7 xor 0x1234,%r25,%r26
|
| pfmam.d | 36 68: 88 a1 d8 4a mrmt1p2.dd %f20,%f22,%f24
42 80: 8a a1 d8 4a mrm1p2.dd %f20,%f22,%f24
64 d8: 01 0a 43 48 d.mr2pt.ss %f1,%f2,%f3
110 190: 88 a3 d8 4a d.mrmt1p2.dd %f20,%f22,%f24
122 1c0: 8a a3 d8 4a d.mrm1p2.dd %f20,%f22,%f24
128 1d8: 8b b3 1a 4b d.mm12ttpm.dd %f22,%f24,%f26
|
| pfmsm.d | 36 68: 98 a1 d8 4a mrmt1s2.dd %f20,%f22,%f24
42 80: 9a a1 d8 4a mrm1s2.dd %f20,%f22,%f24
64 d8: 11 0a 43 48 d.mr2st.ss %f1,%f2,%f3
110 190: 98 a3 d8 4a d.mrmt1s2.dd %f20,%f22,%f24
122 1c0: 9a a3 d8 4a d.mrm1s2.dd %f20,%f22,%f24
128 1d8: 9b b3 1a 4b d.mm12ttsm.dd %f22,%f24,%f26
|
| /external/libavc/common/arm/ |
| ih264_ihadamard_scaling_a9.s | 109 vpush {d8-d15}
126 vswp d5, d8 @Q2 = x4, Q4 = x6
158 vpop {d8-d15}
218 vpush {d8-d15}
247 vpop {d8-d15}
|
| ih264_inter_pred_luma_horz_hpel_vert_hpel_a9q.s | 118 vstmdb sp!, {d8-d15} @push neon registers to stack
138 vld1.u32 {d8, d9, d10}, [r0], r2 @ Vector load from src[2_0]
144 vaddl.u8 q10, d8, d11 @ temp1 = src[2_0] + src[3_0]
205 vaddl.u8 q11, d8, d17 @ temp = src[1_0] + src[4_0]
271 vld1.u32 {d8, d9}, [r0], r2 @ Vector load from src[3_0]
276 vaddl.u8 q10, d6, d8 @ temp1 = src[2_0] + src[3_0]
310 vaddl.u8 q10, d8, d10 @ temp1 = src[2_0] + src[3_0]
355 vld1.u32 {d8, d9}, [r0], r2 @ Vector load from src[3_0]
360 vaddl.u8 q10, d6, d8 @ temp1 = src[2_0] + src[3_0]
396 vaddl.u8 q10, d8, d10 @ temp1 = src[2_0] + src[3_0
[all...] |
| ih264_inter_pred_filters_luma_vert_a9q.s | 106 vstmdb sp!, {d8-d15} @push neon registers to stack
130 vaddl.u8 q8, d2, d8 @ temp2 = src[1_0] + src[4_0]
137 vaddl.u8 q6, d6, d8
152 vaddl.u8 q6, d8, d10
169 vaddl.u8 q10, d8, d2
188 vaddl.u8 q7, d8, d6 @ temp = src[0_0] + src[5_0]
298 vldmia sp!, {d8-d15} @ Restore neon registers that were saved
|
| ih264_inter_pred_luma_horz_qpel_vert_hpel_a9q.s | 123 vstmdb sp!, {d8-d15} @push neon registers to stack
169 vaddl.u8 q11, d2, d8
239 vaddl.u8 q10, d6, d8
331 vaddl.u8 q8, d2, d8
339 vaddl.u8 q8, d6, d8
370 vaddl.u8 q8, d8, d10
422 vaddl.u8 q8, d2, d8 @ temp2 = src[1_0] + src[4_0]
430 vaddl.u8 q8, d6, d8
461 vaddl.u8 q8, d8, d10
502 vldmia sp!, {d8-d15} @ Restore neon registers that were save
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/ |
| operands.d | 64 0+0d8 <foo\+(0x|)d8> tstl %a0@\(0+3e8,%d0:w:2\)
105 0+1d8 <foo\+(0x|)1d8> tstl %a0@\(0+3e8\)@\(0+7d0\)
148 0+2ce <foo\+(0x|)2ce> pea %pc@\(0+2d8 <foo\+(0x|)2d8>,%d0:l\)
150 0+2d6 <foo\+(0x|)2d6> pea %pc@\(0+2d8 <foo\+(0x|)2d8>,%d0:w:2\)
230 0+4d8 <foo\+(0x|)4d8> pea %zpc@\(0+000,%a0:l\)@\(0+7d0\
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| vfp1.d | 64 0+0d8 <[^>]*> eeb10b42 (vneg\.f64|fnegd) d0, d2
128 0+1d8 <[^>]*> ec902b1c vldmia r0, {d2-d15}
140 0+208 <[^>]*> eeb58b40 (vcmp\.f64 d8, #0.0|fcmpzd d8)
155 0+244 <[^>]*> 0eb18bca (vsqrteq\.f64|fsqrtdeq) d8, d10
161 0+25c <[^>]*> 0e098b4a (vmlseq\.f64|fnmacdeq) d8, d9, d10
192 0+2d8 <[^>]*> e1a00000 ? nop[ ]+; \(mov r0, r0\)
|
| /external/libjpeg-turbo/simd/ |
| jsimd_arm_neon.S | 261 vpush {d8-d15} /* save NEON registers */
339 vadd.s16 d8, ROW5R, ROW1R
343 vmlal.s16 q6, d8, XFIX_1_175875602
346 vmlal.s16 q7, d8, XFIX_1_175875602_MINUS_0_390180644
506 vpop {d8-d15} /* restore NEON registers */
[all...] |
| /external/valgrind/none/tests/arm/ |
| neon64.c | 672 TESTINSN_imm("vorr.i32 d8", d8, 0x700);
682 TESTINSN_imm("vbic.i16 d8", d8, 0x700);
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| altivec.d | 64 d8: (11 34 fb 8a|8a fb 34 11) vctuxs v9,v31,20
74 100: (11 d8 ac 46|46 ac d8 11) vcmpequh\. v14,v24,v21
80 118: (11 d8 3e c6|c6 3e d8 11) vcmpgtfp\. v14,v24,v7
128 1d8: (12 ff 67 a4|a4 67 ff 12) vmsumubm v23,v31,v12,v30
185 2bc: (12 d8 a0 4a|4a a0 d8 12) vsubfp v22,v24,v20
192 2d8: (13 cb 4e 40|40 4e cb 13) vsubuhs v30,v11,v9
|
| /external/libhevc/common/arm/ |
| ihevc_intra_pred_chroma_mode_27_to_33.s | 163 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
175 vmull.u8 q5,d8,d30 @(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
214 vld1.8 {d8},[r10],r11 @(v)ref_main_idx
236 vmull.u8 q5,d8,d30 @(v)vmull_u8(ref_main_idx, dup_const_32_fract)
291 vld1.8 {d8},[r10],r11 @(i)ref_main_idx
313 vmull.u8 q5,d8,d30 @(i)vmull_u8(ref_main_idx, dup_const_32_fract)
371 vld1.8 {d8},[r10],r11 @(v)ref_main_idx
388 vmull.u8 q5,d8,d30 @(v)vmull_u8(ref_main_idx, dup_const_32_fract)
480 vld1.8 {d8},[r10] @ref_main_idx
495 vmull.u8 q5,d8,d7 @vmull_u8(ref_main_idx, dup_const_32_fract
[all...] |
| ihevc_intra_pred_filters_luma_mode_19_to_25.s | 276 vld1.8 {d8},[r10],r11 @(i row)ref_main_idx
287 vmull.u8 q5,d8,d30 @(i row)vmull_u8(ref_main_idx, dup_const_32_fract)
324 vld1.8 {d8},[r10],r11 @(v)ref_main_idx
344 vmull.u8 q5,d8,d30 @(v)vmull_u8(ref_main_idx, dup_const_32_fract)
397 vld1.8 {d8},[r10],r11 @(i)ref_main_idx
420 vmull.u8 q5,d8,d30 @(i)vmull_u8(ref_main_idx, dup_const_32_fract)
480 vld1.8 {d8},[r10],r11 @(v)ref_main_idx
496 vmull.u8 q5,d8,d30 @(v)vmull_u8(ref_main_idx, dup_const_32_fract)
588 vld1.32 {d8[0]},[r10] @ref_main_idx
603 vmull.u8 q5,d8,d7 @vmull_u8(ref_main_idx, dup_const_32_fract
[all...] |
