| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| guard.d | 10 0: 08001083 88001083 add.s r1, r2, r3 -> add.s r1, r2, r3
11 8: 18001083 a8001083 add.s/tx r1, r2, r3 -> add.s/fx r1, r2, r3
12 10: 38001083 c8001083 add.s/xt r1, r2, r3 -> add.s/xf r1, r2, r3
13 18: 58001083 e8001083 add.s/tt r1, r2, r3 -> add.s/tf r1, r2, r3
14 20: 08001083 88001083 add.s r1, r2, r3 -> add.s r1, r2, r
[all...] |
| guard-debug.d | 11 0: 08001083 00f00000 add.s r1, r2, r3 || nop
13 8: 08001083 00f00000 add.s r1, r2, r3 || nop
15 10: 18001083 00f00000 add.s/tx r1, r2, r3 || nop
17 18: 28001083 00f00000 add.s/fx r1, r2, r3 || nop
19 20: 38001083 00f00000 add.s/xt r1, r2, r3 || nop
21 28: 48001083 00f00000 add.s/xf r1, r2, r3 || nop
23 30: 58001083 00f00000 add.s/tt r1, r2, r3 || nop
25 38: 68001083 00f00000 add.s/tf r1, r2, r3 || nop
|
| guard-debug.s | 7 add r1,r2,r3
8 add/al r1,r2,r3
9 add/tx r1,r2,r3
10 add/fx r1,r2,r3
11 add/xt r1,r2,r3
12 add/xf r1,r2,r3
13 add/tt r1,r2,r3
14 add/tf r1,r2,r3
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m32r/ |
| m32r2.s | 35 btst #1,fp || mv r0,r2
36 mv r0,r2 || btst #1,fp
76 sll r0,r1 || sll r2,r3
77 mul r0,r1 || sll r2,r3
78 sll r0,r1 || mul r2,r3
79 ldi r0,#1 || sll r2,r3
80 sll r0,r1 || ldi r2,#1
85 slli r0,#1 || slli r2,#31
86 mul r0,r1 || slli r2,#31
87 slli r0,#1 || mul r2,r
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| vfp11-fix-vector.s | 6 mov r2,r3
7 flds s14, [r2]
|
| /external/valgrind/coregrind/m_dispatch/ |
| dispatch-arm-linux.S | 64 r2 holds host_addr
82 bx r2
90 /* At this point, r1 and r2 contain two
92 holds a TRC value, and r2 optionally may
105 movw r2, #0
113 str r2, [r0, #4]
128 mov r2, lr
132 sub r2, r2, #4+4+4
143 mov r2, l
[all...] |
| /external/llvm/test/MC/ARM/ |
| v7k-dsp.s | 3 @ CHECK: usad8 r2, r1, r4
4 usad8 r2, r1, r4
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| ldrd-unpredictable.s | 8 ldrd r0,r1,[r0,r2]! @ ditto
9 ldrd r0,r1,[r1,r2]! @ ditto
13 strd r0,r1,[r0,r2]! @ ditto
14 strd r0,r1,[r1,r2]! @ ditto
|
| push-pop.s | 4 push {r1, r2, r3}
7 pop {r1, r2, r3}
|
| inst.s | 6 mov r1, r2
19 movcc r1, r2
33 add r2, r3, r4
35 add r1, r2, r3, lsl r1
38 and r2, r3, r4
40 and r1, r2, r3, lsl r1
43 eor r2, r3, r4
45 eor r1, r2, r3, lsl r1
48 sub r2, r3, r4
50 sub r1, r2, r3, lsl r
[all...] |
| arch7em.s | 14 pkhtb r1, r2, r3
15 pkhtb r1, r2, r3, asr #0x11
18 qadd r1, r2, r3
19 qadd16 r1, r2, r3
20 qadd8 r1, r2, r3
21 qasx r1, r2, r3
22 qaddsubx r1, r2, r3
23 qdadd r1, r2, r3
24 qdsub r1, r2, r3
25 qsub r1, r2, r
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ia64/ |
| alloc.s | 7 alloc r2 = ar.pfs, x, 0, 0, 0
8 alloc r2 = ar.pfs, 0, x, 0, 0
9 alloc r2 = ar.pfs, 0, 0, x, 0
10 alloc r2 = ar.pfs, 0, 0, 0, x
|
| /external/libhevc/common/arm/ |
| ihevc_deblk_chroma_vert.s | 62 add r2,r2,r3
64 add r2,r2,#1
72 adds r3,r7,r2,asr #1
85 adds r2,r6,r2,asr #1
88 cmp r2,#0x39
89 ldrle r2,[r7,r2,lsl #2
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| residu_asm_opt.s | 25 @y[] --- r2
72 MOV r0, r2
78 LDR r2, [r1], #-4 @r2 --- x[1], x[0]
80 SMULTB r3, r5, r2 @i1(0) --- r3 = x[0] * a0
81 SMULTT r4, r5, r2 @i2(0) --- r4 = x[1] * a0
85 SMLABB r4, r5, r2, r4 @i2(1) --- r4 += x[0] * a1
86 SMLABT r11, r5, r2, r11 @i3(1) --- r11 += x[1] * a0
89 SMLATB r11, r6, r2, r11 @i3(2) --- r11 += x[0] * a2
90 SMLATT r12, r6, r2, r12 @i4(2) --- r12 += x[1] * a
[all...] |
| /art/runtime/interpreter/mterp/arm/ |
| op_move.S | 7 GET_VREG r2, r1 @ r2<- fp[B]
10 SET_VREG_OBJECT r2, r0 @ fp[A]<- r2
12 SET_VREG r2, r0 @ fp[A]<- r2
|
| op_move_16.S | 7 GET_VREG r2, r1 @ r2<- fp[BBBB]
10 SET_VREG_OBJECT r2, r0 @ fp[AAAA]<- r2
12 SET_VREG r2, r0 @ fp[AAAA]<- r2
|
| op_move_from16.S | 7 GET_VREG r2, r1 @ r2<- fp[BBBB]
10 SET_VREG_OBJECT r2, r0 @ fp[AA]<- r2
12 SET_VREG r2, r0 @ fp[AA]<- r2
|
| /external/valgrind/none/tests/s390x/ |
| bfp-1.c | 32 register float r2 asm("f2") = f2;
34 __asm__ volatile ("aebr %[r1],%[r2]\n\t"
36 : [r2] "f"(r2) : "cc");
43 register float r2 asm("f2") = f2;
45 __asm__ volatile ("sebr %[r1],%[r2]\n\t"
47 : [r2] "f"(r2) : "cc");
54 register float r2 asm("f2") = f2;
56 __asm__ volatile ("meebr %[r1],%[r2]\n\t
[all...] |
| /frameworks/native/opengl/libagl/ |
| fixed_asm.S | 37 mov r2, #0x8E /* 127 + 15 */
38 sub r1, r2, r1, lsr #24 /* compute shift */
39 mov r2, r0, lsl #8 /* mantissa<<8 */
40 orr r2, r2, #0x80000000 /* add the missing 1 */
41 mov r0, r2, lsr r1 /* scale to 16.16 */
52 mov r2, #0x8E /* 127 + 15 */
53 subs r1, r2, r1, lsr #24 /* compute shift */
55 mov r2, r0, lsl #8 /* mantissa<<8 */
56 orr r2, r2, #0x80000000 /* add the missing 1 *
[all...] |
| /toolchain/binutils/binutils-2.25/binutils/testsuite/binutils-all/ |
| link-order.s | 7 .vframe r2
8 mov r2 = r12
11 mov r12 = r2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d10v/ |
| instruction_packing-002.s | 7 add r2,r11 || add r3,r11
8 add r2,r11 -> add r3,r11
9 add r2,r11 <- add r3,r11
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| custom.s | 4 custom 0, r11, r2, r3
5 custom 255, r11, r2, r3
6 custom 150, c1, r2, r3
|
| movi.d | 8 0+0000 <[^>]*> 00800804 movi r2,32
9 0+0004 <[^>]*> 00880034 movhi r2,8192
10 0+0008 <[^>]*> 00bffff4 movhi r2,65535
11 0+000c <[^>]*> 28bffff4 orhi r2,r5,65535
12 0+0010 <[^>]*> 50bffffc xorhi r2,r10,65535
13 0+0014 <[^>]*> 78bfffec andhi r2,r15,65535
|
| movia.d | 9 0+0000 <[^>]*> 00a02074 movhi r2,32897
10 0+0004 <[^>]*> 10a02004 addi r2,r2,-32640
19 0+0018 <[^>]*> 00800034 movhi r2,0
20 0+001c <[^>]*> 10bffc04 addi r2,r2,-16
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/ |
| zarch-operands.s | 3 .insn rie,0xec0000000045,%r1,%r2,test_rie
5 .insn rse,0xeb000000000d,%r1,%r2,3(%r4)
6 .insn ssf,0xc80000000000,1(%r2),3(%r4),%r5
|
