| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/s390/ |
| zarch-z9-ec.s | 7 ldgr %f6,%r2
8 lgdr %r2,%f6
17 cdgtr %f6,%r2
18 cxgtr %f1,%r2
19 cdstr %f6,%r2
20 cxstr %f6,%r2
21 cdutr %f6,%r2
22 cxutr %f1,%r2
23 cgdtr %r2,1,%f6
24 cgxtr %r2,1,%f
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| mov_test.s | 8 movb $0xff,r2
10 #movb $0xffff,r2 // CHECK WITH CRASM 4.1
12 movb $10,r2
13 movb $11,r2
17 movb r1,r2
18 movb r2,r3
28 movw $0xff,r2
30 #movw $0xffff,r2 // CHECK WITH CRASM 4.1
32 movw $10,r2
33 movw $11,r2
[all...] |
| cmp_test.d | 11 2: b2 50 ff 00 cmpb \$0xff:m,r2
14 e: a2 50 cmpb \$0xa:s,r2
15 10: b2 50 0b 00 cmpb \$0xb:m,r2
16 14: 12 51 cmpb r1,r2
17 16: 23 51 cmpb r2,r3
24 26: b2 52 ff 00 cmpw \$0xff:m,r2
27 32: a2 52 cmpw \$0xa:s,r2
28 34: b2 52 0b 00 cmpw \$0xb:m,r2
29 38: 12 53 cmpw r1,r2
30 3a: 23 53 cmpw r2,r
[all...] |
| sub_test.d | 11 2: b2 38 ff 00 subb \$0xff:m,r2
14 e: a2 38 subb \$0xa:s,r2
15 10: 12 39 subb r1,r2
16 12: 23 39 subb r2,r3
22 1e: b2 3c ff 00 subcb \$0xff:m,r2
25 2a: a2 3c subcb \$0xa:s,r2
26 2c: 12 3d subcb r1,r2
27 2e: 23 3d subcb r2,r3
33 3a: b2 3e ff 00 subcw \$0xff:m,r2
36 46: a2 3e subcw \$0xa:s,r2
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| ldr.d | 8 0+04 <[^>]+> e5b21005 ldr r1, \[r2, #5\]!
14 0+1c <[^>]+> e7911002 ldr r1, \[r1, r2\]
15 0+20 <[^>]+> e79f2002 ldr r2, \[pc, r2\]
16 0+24 <[^>]+> e7b21003 ldr r1, \[r2, r3\]!
20 0+34 <[^>]+> e5a2100a str r1, \[r2, #10\]!
21 0+38 <[^>]+> e7811002 str r1, \[r1, r2\]
22 0+3c <[^>]+> e78f1002 str r1, \[pc, r2\]
23 0+40 <[^>]+> e7a21003 str r1, \[r2, r3\]!
|
| ldr-bad.s | 15 ldr r1, [r1, r2]!
16 ldr r2, [r15, r2]!
26 str r1, [r1, r2]!
27 str r1, [r15, r2]!
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d30v/ |
| array.d | 10 0: 880820c0 80000048 add.l r2, r3, 0x48
12 8: 880820c0 80000049 add.l r2, r3, 0x49
14 10: 880820c0 8000004a add.l r2, r3, 0x4a
16 18: 880820c0 8000004b add.l r2, r3, 0x4b
18 20: 880820c0 8000004c add.l r2, r3, 0x4c
20 28: 880820c0 8000004d add.l r2, r3, 0x4d
22 30: 880820c0 8000004e add.l r2, r3, 0x4e
24 38: 880820c0 8000004f add.l r2, r3, 0x4f
26 40: 880820c0 80000050 add.l r2, r3, 0x50
|
| serial.s | 6 trap r21 -> add r2, r0, r0 ; right instruction will never be executed.
7 dbt -> add r2, r0, r0 ; ditto
8 rtd -> add r2, r0, r0 ; ditto
9 reit -> add r2, r0, r0 ; ditto
10 mvtsys psw, r1 -> add r2, r0, r0 ; OK
11 mvtsys pswh, r1 -> add r2, r0, r0 ; OK
12 mvtsys pswl, r1 -> add r2, r0, r0 ; OK
13 mvtsys f0, r1 -> add r2, r0, r0 ; OK
14 mvtsys mod_s, r1 -> add r2, r0, r0 ; OK
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cris/ |
| binop.d | 102 [ ]+18c:[ ]+4205 @IM+055a@[ ]+@OC@\.b \[\$?r2\+\$?r0\.b\],\$?r5
103 [ ]+190:[ ]+4255 @IM+1dda@[ ]+@OC@\.w \[\$?r2\+\$?r5\.b\],\$?r13
104 [ ]+194:[ ]+42a5 @IM+211a@[ ]+@OC@\.d \[\$?r2\+\$?r10\.b\],\$?r1
105 [ ]+198:[ ]+4029 @IM+055a@[ ]+@OC@\.b \[\$?r2\+\[\$?r0\]\.b\],\$?r5
106 [ ]+19c:[ ]+4529 @IM+1dda@[ ]+@OC@\.w \[\$?r2\+\[\$?r5\]\.b\],\$?r13
107 [ ]+1a0:[ ]+4a29 @IM+211a@[ ]+@OC@\.d \[\$?r2\+\[\$?r10\]\.b\],\$?r1
108 [ ]+1a4:[ ]+402d @IM+055a@[ ]+@OC@\.b \[\$?r2\+\[\$?r0\+\]\.b\],\$?r5
109 [ ]+1a8:[ ]+452d @IM+1dda@[ ]+@OC@\.w \[\$?r2\+\[\$?r5\+\]\.b\],\$?r13
110 [ ]+1ac:[ ]+4a2d @IM+211a@[ ]+@OC@\.d \[\$?r2\+\[\$?r10\+\]\.b\],\$?r1
111 [ ]+1b0:[ ]+452d @IM+1dda@[ ]+@OC@\.w \[\$?r2\+\[\$?r5\+\]\.b\],\$?r1
[all...] |
| /art/runtime/interpreter/mterp/arm/ |
| op_iput.S | 13 ubfx r2, rINST, #8, #4 @ r2<- A
14 GET_VREG r2, r2 @ r2<- fp[A]
|
| op_iput_wide.S | 7 ubfx r2, rINST, #8, #4 @ r2<- A
8 VREG_INDEX_TO_ADDR r2, r2 @ r2<- &fp[A]
|
| op_move_wide_16.S | 4 FETCH r2, 1 @ r2<- AAAA
6 VREG_INDEX_TO_ADDR lr, r2 @ r2<- &fp[AAAA]
9 CLEAR_SHADOW_PAIR r2, r3, ip @ Zero out the shadow regs
|
| op_sget.S | 13 mov r2, rSELF
16 mov r2, rINST, lsr #8 @ r2<- AA
21 SET_VREG_OBJECT r0, r2 @ fp[AA]<- r0
23 SET_VREG r0, r2 @ fp[AA]<- r0
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
| ld.d | 9 0: 00 84 00 00 00008400 ld r0,\[r1,r2\]
10 4: 02 84 00 00 00008402 ldb r0,\[r1,r2\]
12 c: 05 06 21 00 00210605 ldw.x r1,\[r2,r3\]
13 10: 0d 88 41 00 0041880d ldw.x.a r2,\[r3,r4\]
16 1c: ec 01 21 08 082101ec ld r1,\[r2,-20\]
|
| adc.s | 3 adc r0,r1,r2
9 adc r0,0,r2
10 adc 0,r1,r2
12 adc r0,-1,r2
13 adc -1,r1,r2
15 adc r0,255,r2
16 adc 255,r1,r2
18 adc r0,-256,r2
19 adc -256,r1,r2
22 adc r0,-257,r2
[all...] |
| add.s | 3 add r0,r1,r2
9 add r0,0,r2
10 add 0,r1,r2
12 add r0,-1,r2
13 add -1,r1,r2
15 add r0,255,r2
16 add 255,r1,r2
18 add r0,-256,r2
19 add -256,r1,r2
22 add r0,-257,r2
[all...] |
| and.s | 3 and r0,r1,r2
9 and r0,0,r2
10 and 0,r1,r2
12 and r0,-1,r2
13 and -1,r1,r2
15 and r0,255,r2
16 and 255,r1,r2
18 and r0,-256,r2
19 and -256,r1,r2
22 and r0,-257,r2
[all...] |
| bic.s | 3 bic r0,r1,r2
9 bic r0,0,r2
10 bic 0,r1,r2
12 bic r0,-1,r2
13 bic -1,r1,r2
15 bic r0,255,r2
16 bic 255,r1,r2
18 bic r0,-256,r2
19 bic -256,r1,r2
22 bic r0,-257,r2
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/v850/ |
| split-lo16.d | 8 4: 01 16 00 00 addi 0, r1, r2
10 8: 01 17 00 00 ld\.b 0\[r1\], r2
12 c: 81 17 01 00 ld\.bu 0\[r1\], r2
14 10: a1 17 45 23 ld\.bu 9029\[r1\], r2
15 14: 81 17 57 34 ld\.bu 13398\[r1\], r2
|
| split-lo16.s | 2 addi lo(foo),r1,r2
3 ld.b lo(foo),r1,r2
4 ld.bu lo(foo),r1,r2
6 ld.bu lo(0x12345),r1,r2
7 ld.bu lo(0x123456),r1,r2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68hc11/ |
| insns9s12xg.s | 11 adc r1,r2,r3
19 and r2,#val2
22 asr r2,#3
27 bfext r1,r2,r3
30 bfinsi r2,r4,r6
36 bith r2,#0x55
49 cmp r1,r2
58 csl r2,#1
63 ldb r2,(r3,#4)
64 ldb r3,(r0,r2)
[all...] |
| /external/valgrind/none/tests/arm/ |
| v6intARM.c | 165 TESTINST3("adds r0, r1, r2", 0, 0, r0, r1, r2, 0);
166 TESTINST3("adds r0, r1, r2", 0, 1, r0, r1, r2, 0);
167 TESTINST3("adds r0, r1, r2", 1, 0, r0, r1, r2, 0);
168 TESTINST3("adds r0, r1, r2", 1, 1, r0, r1, r2, 0);
169 TESTINST3("adds r0, r1, r2", 0, -1, r0, r1, r2, 0)
[all...] |
| /external/libvpx/libvpx/vp8/encoder/arm/armv6/ |
| walsh_v6.asm | 22 ; r2 int pitch
27 ldrd r4, r5, [r0], r2
29 ldrd r6, r7, [r0], r2
35 ldrd r8, r9, [r0], r2
50 lsls r2, r3, #16
54 lsls r2, r7, #16
61 lsls r2, r5, #16
65 lsls r2, r9, #16
66 smuad r2, r9, lr ; D0 = a1<<2 + d1<<2
67 addne r2, r2, #1 ; D0 += (a1!=0
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp8/encoder/arm/armv6/ |
| walsh_v6.asm | 22 ; r2 int pitch
27 ldrd r4, r5, [r0], r2
29 ldrd r6, r7, [r0], r2
35 ldrd r8, r9, [r0], r2
50 lsls r2, r3, #16
54 lsls r2, r7, #16
61 lsls r2, r5, #16
65 lsls r2, r9, #16
66 smuad r2, r9, lr ; D0 = a1<<2 + d1<<2
67 addne r2, r2, #1 ; D0 += (a1!=0
[all...] |
| /bionic/libc/arch-arm/cortex-a9/bionic/ |
| memcpy_base.S | 41 cmp r2, #16
50 cmp r2, #224
59 sub r2, r2, r3
84 subs r2, r2, #64
95 subs r2, r2, #64
101 add r2, r2, #6
[all...] |
