| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arc/ |
| or.s | 3 or r0,r1,r2
9 or r0,0,r2
10 or 0,r1,r2
12 or r0,-1,r2
13 or -1,r1,r2
15 or r0,255,r2
16 or 255,r1,r2
18 or r0,-256,r2
19 or -256,r1,r2
22 or r0,-257,r2
[all...] |
| sbc.s | 3 sbc r0,r1,r2
9 sbc r0,0,r2
10 sbc 0,r1,r2
12 sbc r0,-1,r2
13 sbc -1,r1,r2
15 sbc r0,255,r2
16 sbc 255,r1,r2
18 sbc r0,-256,r2
19 sbc -256,r1,r2
22 sbc r0,-257,r2
[all...] |
| sub.s | 3 sub r0,r1,r2
9 sub r0,0,r2
10 sub 0,r1,r2
12 sub r0,-1,r2
13 sub -1,r1,r2
15 sub r0,255,r2
16 sub 255,r1,r2
18 sub r0,-256,r2
19 sub -256,r1,r2
22 sub r0,-257,r2
[all...] |
| xor.s | 3 xor r0,r1,r2
9 xor r0,0,r2
10 xor 0,r1,r2
12 xor r0,-1,r2
13 xor -1,r1,r2
15 xor r0,255,r2
16 xor 255,r1,r2
18 xor r0,-256,r2
19 xor -256,r1,r2
22 xor r0,-257,r2
[all...] |
| ld2.s | 6 ld.a r4,[r2,10]
8 ldb r2,[r3,15]
11 lr r1,[r2]
|
| st.d | 9 0: 00 02 01 10 10010200 st r1,\[r2\]
10 4: 0e 02 01 10 1001020e st r1,\[r2,14\]
11 8: 00 02 41 10 10410200 stb r1,\[r2\]
13 10: 02 02 81 11 11810202 stw.a r1,\[r2,2\]
16 1c: 00 7e 41 10 10417e00 stb 0,\[r2\]
17 20: f8 7f 01 10 10017ff8 st -8,\[r2,-8\]
20 2c: 00 04 1f 10 101f0400 st r2,\[0\]
23 34: 02 02 01 14 14010202 st.di r1,\[r2,2\]
24 38: 03 02 01 15 15010203 st.a.di r1,\[r2,3\]
25 3c: 04 02 81 15 15810204 stw.a.di r1,\[r2,4\
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/cr16/ |
| and_test.d | 11 2: b2 20 ff 00 andb \$0xff:m,r2
13 a: b2 20 ff ff andb \$0xffff:m,r2
15 12: a2 20 andb \$0xa:s,r2
16 14: 12 21 andb r1,r2
17 16: 23 21 andb r2,r3
23 22: b2 22 ff 00 andw \$0xff:m,r2
25 2a: b2 22 ff ff andw \$0xffff:m,r2
27 32: a2 22 andw \$0xa:s,r2
28 34: 12 23 andw r1,r2
29 36: 23 23 andw r2,r
[all...] |
| or_test.d | 11 2: b2 24 ff 00 orb \$0xff:m,r2
13 a: b2 24 ff ff orb \$0xffff:m,r2
15 12: a2 24 orb \$0xa:s,r2
16 14: 12 25 orb r1,r2
17 16: 23 25 orb r2,r3
23 22: b2 26 ff 00 orw \$0xff:m,r2
25 2a: b2 26 ff ff orw \$0xffff:m,r2
27 32: a2 26 orw \$0xa:s,r2
28 34: 12 27 orw r1,r2
29 36: 23 27 orw r2,r
[all...] |
| xor_test.d | 11 2: b2 28 ff 00 xorb \$0xff:m,r2
13 a: b2 28 ff ff xorb \$0xffff:m,r2
15 12: a2 28 xorb \$0xa:s,r2
16 14: 12 29 xorb r1,r2
17 16: 23 29 xorb r2,r3
23 22: b2 2a ff 00 xorw \$0xff:m,r2
25 2a: b2 2a ff ff xorw \$0xffff:m,r2
27 32: a2 2a xorw \$0xa:s,r2
28 34: 12 2b xorw r1,r2
29 36: 23 2b xorw r2,r
[all...] |
| /art/runtime/interpreter/mterp/arm/ |
| op_monitor_enter.S | 6 mov r2, rINST, lsr #8 @ r2<- AA
7 GET_VREG r0, r2 @ r0<- vAA (object)
|
| op_return.S | 13 mov r2, rINST, lsr #8 @ r2<- AA
14 GET_VREG r0, r2 @ r0<- vAA
|
| op_sput_wide.S | 10 mov r2, rINST, lsr #8 @ r3<- AA
11 VREG_INDEX_TO_ADDR r2, r2
|
| op_throw.S | 6 mov r2, rINST, lsr #8 @ r2<- AA
7 GET_VREG r1, r2 @ r1<- vAA (exception object)
|
| /external/compiler-rt/lib/builtins/arm/ |
| aeabi_memset.S | 18 mov r1, r2
19 mov r2, r3
27 mov r2, r1
|
| /external/libcxx/test/std/utilities/function.objects/refwrap/refwrap.assign/ |
| copy_assign.pass.cpp | 30 std::reference_wrapper<T> r2(t2);
31 r2 = r;
32 assert(&r2.get() == &t);
42 std::reference_wrapper<void ()> r2(g);
43 r2 = r;
44 assert(&r2.get() == &f);
|
| /external/llvm/test/MC/ARM/ |
| arm-aliases.s | 5 add r1, r2, r3, lsl #0
6 sub r1, r2, r3, ror #0
7 eor r1, r2, r3, lsr #0
8 orr r1, r2, r3, asr #0
9 and r1, r2, r3, ror #0
10 bic r1, r2, r3, lsl #0
12 @ CHECK: add r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe0]
13 @ CHECK: sub r1, r2, r3 @ encoding: [0x03,0x10,0x42,0xe0]
14 @ CHECK: eor r1, r2, r3 @ encoding: [0x03,0x10,0x22,0xe0]
15 @ CHECK: orr r1, r2, r3 @ encoding: [0x03,0x10,0x82,0xe1
[all...] |
| /ndk/sources/cxx-stl/llvm-libc++/libcxx/test/utilities/function.objects/refwrap/refwrap.assign/ |
| copy_assign.pass.cpp | 30 std::reference_wrapper<T> r2(t2);
31 r2 = r;
32 assert(&r2.get() == &t);
42 std::reference_wrapper<void ()> r2(g);
43 r2 = r;
44 assert(&r2.get() == &f);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| arm7t.s | 7 ldrh r0, [r1, r2]
8 ldrh r0, [r1, r2]!
12 ldrh r0, [r1], r2
20 strh r0, [r1, r2]
21 strh r0, [r1, r2]!
25 strh r0, [r1], r2
31 ldrsb r0, [r1, r2]
32 ldrsb r0, [r1, r2]!
36 ldrsb r0, [r1], r2
43 ldrsh r0, [r1, r2]
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/d10v/ |
| instruction_packing-005.s | 24 mv r2,r0
27 and3 r1,r2,-32768
29 slli r2,1
31 mv r0,r2
33 mvf0t r2,r0
36 mv r0,r2
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/nios2/ |
| complex.d | 9 0+0000 <[^>]*> 18bfffd7 ldw r2,-1\(r3\)
10 0+0004 <[^>]*> 18800057 ldw r2,1\(r3\)
11 0+0008 <[^>]*> 18800017 ldw r2,0\(r3\)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/ppc/ |
| e6500.d | 13 c: (7c 01 10 dc|dc 10 01 7c) mvidsplt v0,r1,r2
14 10: (7c 01 10 5c|5c 10 01 7c) mviwsplt v0,r1,r2
15 14: (7c 00 12 0a|0a 12 00 7c) lvexbx v0,0,r2
16 18: (7c 01 12 0a|0a 12 01 7c) lvexbx v0,r1,r2
17 1c: (7c 00 12 4a|4a 12 00 7c) lvexhx v0,0,r2
18 20: (7c 01 12 4a|4a 12 01 7c) lvexhx v0,r1,r2
19 24: (7c 00 12 8a|8a 12 00 7c) lvexwx v0,0,r2
20 28: (7c 01 12 8a|8a 12 01 7c) lvexwx v0,r1,r2
21 2c: (7c 00 13 0a|0a 13 00 7c) stvexbx v0,0,r2
22 30: (7c 01 13 0a|0a 13 01 7c) stvexbx v0,r1,r2
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-arm/ |
| data-only-map.d | 8 0: eb01 0002 add\.w r0, r1, r2
10 8: eb01 0002 add\.w r0, r1, r2
11 c: eb01 0200 add\.w r2, r1, r0
|
| cortex-a8-fix-blx.d | 8 8f00: e1a02413 lsl r2, r3, r4
13 8f0a: eb01 0002 add\.w r0, r1, r2
15 8f12: eb01 0002 add\.w r0, r1, r2
17 8f1a: eb01 0002 add\.w r0, r1, r2
19 8f22: eb01 0002 add\.w r0, r1, r2
21 8f2a: eb01 0002 add\.w r0, r1, r2
23 8f32: eb01 0002 add\.w r0, r1, r2
25 8f3a: eb01 0002 add\.w r0, r1, r2
27 8f42: eb01 0002 add\.w r0, r1, r2
29 8f4a: eb01 0002 add\.w r0, r1, r2
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-powerpc/ |
| tls32.d | 13 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
15 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
17 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
19 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
24 .*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
26 .*: (89 42 90 34|34 90 42 89) lbz r10,-28620\(r2\)
27 .*: (3d 22 00 00|00 00 22 3d) addis r9,r2,0
29 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
31 .*: (3c 62 00 00|00 00 62 3c) addis r3,r2,0
36 .*: (3d 22 00 00|00 00 22 3d) addis r9,r2,
[all...] |
| /toolchain/binutils/binutils-2.25/ld/testsuite/ld-tilegx/ |
| reloc.s | 4 add r2,zero,zero
7 add r3,r2,r2
10 { movei r2,external_8a; movei r3,external_8b }
11 { movei r2,external_8a; movei r3,external_8b; ld zero,zero }
14 { moveli r2,external_16a; moveli r3,external_16b }
16 { moveli r2,hw1_last(external_32a); moveli r3,hw1_last(external_32b) }
17 { shl16insli r2,r2,hw0(external_32a); shl16insli r3,r3,hw0(external_32b) }
19 { moveli r2,hw2_last(external_48a); moveli r3,hw2_last(external_48b)
[all...] |
