| /external/clang/lib/CodeGen/ |
| CGStmtOpenMP.cpp | [all...] |
| TargetInfo.cpp | 50 // Alignment and Size are measured in bits.
52 const uint64_t Alignment = Context.getTypeAlign(Ty);
53 llvm::Type *IntType = llvm::Type::getIntNTy(LLVMContext, Alignment);
54 const uint64_t NumElements = (Size + Alignment - 1) / Alignment;
190 // Dynamically round a pointer up to a multiple of the given alignment.
212 /// \param SlotSize - The size and alignment of a stack slot.
215 /// \param AllowHigherAlign - The slot alignment is not a cap;
216 /// an argument type with an alignment greater than the slot size
217 /// will be emitted on a higher-alignment address, potentiall
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_2_7/ |
| BitcodeReader.cpp | 816 // The alignment is stored as a 16-bit raw value from bits 31--16. We shift
818 unsigned Alignment = (EncodedAttrs & (0xffffULL << 16)) >> 16;
819 assert((!Alignment || isPowerOf2_32(Alignment)) &&
820 "Alignment must be a power of two.");
822 if (Alignment)
823 B.addAlignmentAttr(Alignment);
[all...] |
| /frameworks/compile/libbcc/bcinfo/BitReader_3_0/ |
| BitcodeReader.cpp | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | [all...] |
| LegalizeVectorOps.cpp | 653 unsigned Alignment = ST->getAlignment();
685 isVolatile, isNonTemporal, MinAlign(Alignment, Idx*Stride),
[all...] |
| /external/llvm/include/llvm/Target/ |
| TargetLowering.h | 497 unsigned align; // alignment
749 /// Return the desired alignment for ByVal or InAlloca aggregate function
750 /// arguments in the caller parameter area. This is the actual alignment, not
[all...] |
| /external/llvm/lib/CodeGen/ |
| TargetLoweringBase.cpp | [all...] |
| CodeGenPrepare.cpp | [all...] |
| /art/runtime/ |
| art_method.h | 646 // Alignment of an instance of this native class.
647 static size_t Alignment(size_t pointer_size) {
648 // The ArtMethod alignment is the same as image pointer size. This differs from
|
| /external/clang/lib/AST/ |
| ExprObjC.cpp | 300 Size, llvm::AlignOf<ObjCMessageExpr>::Alignment);
|
| DeclObjC.cpp | [all...] |
| /external/llvm/lib/Object/ |
| COFFYAML.cpp | 490 IO.mapOptional("Alignment", Sec.Alignment);
|
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | [all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| dsdriver.h | 123 ULONGLONG Alignment;
|
| /external/llvm/lib/IR/ |
| Metadata.cpp | 388 llvm::AlignOf<uint64_t>::Alignment >= llvm::AlignOf<CLASS>::Alignment, \
389 "Alignment is insufficient after objects prepended to " #CLASS);
[all...] |
| /external/v8/src/ia32/ |
| codegen-ia32.cc | 72 enum Alignment { MOVE_ALIGNED, MOVE_UNALIGNED };
75 // esi - source, aligned if alignment == ALIGNED
82 Alignment alignment) {
93 __ movdq(alignment == MOVE_ALIGNED, xmm0, Operand(src, 0x00));
94 __ movdq(alignment == MOVE_ALIGNED, xmm1, Operand(src, 0x10));
95 __ movdq(alignment == MOVE_ALIGNED, xmm2, Operand(src, 0x20));
96 __ movdq(alignment == MOVE_ALIGNED, xmm3, Operand(src, 0x30));
111 __ movdq(alignment == MOVE_ALIGNED, xmm0, Operand(src, 0x00));
112 __ movdq(alignment == MOVE_ALIGNED, xmm1, Operand(src, 0x10))
[all...] |
| /external/llvm/bindings/ocaml/llvm/ |
| llvm.ml | 102 | Alignment of int
590 external alignment : llvalue -> int = "llvm_alignment"
763 | Attribute.Alignment n -> Int32.shift_left (Int32.of_int n) 16
801 l := Attribute.Alignment (Int32.to_int align) :: !l;
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelLowering.cpp | 527 /// by "Src" to address "Dst" of size "Size". Alignment information is
723 // Record if we need > 8 byte alignment on an argument.
778 // V6 vectors passed by value have 64 or 128 byte alignment depending
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | [all...] |
| /external/llvm/include/llvm/IR/ |
| IRBuilder.h | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFrameLowering.cpp | 239 const unsigned Alignment,
244 const unsigned AlignMask = Alignment - 1;
245 const unsigned NrBitsToZero = countTrailingZeros(Alignment);
250 // bfc Reg, #0, log2(Alignment)
253 // bic Reg, Reg, Alignment-1
255 // lsr Reg, Reg, log2(Alignment)
256 // lsl Reg, Reg, log2(Alignment)
269 "instruction to be emitted for large stack alignment for a target "
418 assert(DPRGapSize == 4 && "unexpected alignment requirements for DPRs");
790 "unexpected DPR alignment gap")
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 633 unsigned Alignment = HexagonMCInstrInfo::getExtentAlignment(MCII, MI);
634 uint32_t Lower6 = static_cast<uint32_t>(Value >> Alignment) & 0x3f;
[all...] |
| /external/mesa3d/src/mesa/main/ |
| attrib.c | [all...] |
