| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.h | 123 case AArch64::D11: return AArch64::B11;
163 case AArch64::B11: return AArch64::D11;
[all...] |
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 104 vld1.8 {d10, d11}, [r1], r3
110 vabal.u8 q1, d11, d9
116 vld1.8 {d10, d11}, [r1], r3
121 vabal.u8 q1, d11, d9
187 vld1.8 {d10, d11}, [r1], r3
193 vabal.u8 q1, d11, d9
199 vld1.8 {d10, d11}, [r1], r3
204 vabal.u8 q1, d11, d9
271 vld1.8 {d10, d11}, [r1], r3
279 vabal.u8 q1, d11, d
[all...] |
| /external/libhevc/common/arm/ |
| ihevc_sao_edge_offset_class2_chroma.s | 335 VLD1.8 D11,[r8] @pu1_top_row = vld1q_u8(pu1_src - src_strd - 2) || vld1q_u8(pu1_src_top_cpy - 2)
[all...] |
| ihevc_sao_edge_offset_class3_chroma.s | 325 VLD1.8 D11,[r8] @pu1_top_row = vld1q_u8(pu1_src - src_strd + 2)
[all...] |
| /external/icu/icu4c/source/data/sprep/ |
| rfc4518.txt | 165 0D11; ; UNASSIGNED
|
| rfc3491.txt | 166 0D11; ; UNASSIGNED
[all...] |
| rfc3530csci.txt | 165 0D11; ; UNASSIGNED
[all...] |
| rfc3722.txt | 166 0D11; ; UNASSIGNED
[all...] |
| rfc3920node.txt | 166 0D11; ; UNASSIGNED
[all...] |
| rfc4518ci.txt | 165 0D11; ; UNASSIGNED
[all...] |
| /external/libavc/common/arm/ |
| ih264_deblk_chroma_a9.s | 122 vrshrn.u16 d11, q14, #2 @Q5 = (X2(p1U) + p0U + q1U + 2) >> 2
126 vst2.8 {d10, d11}, [r4], r1 @
420 vtbl.8 d13, {d24}, d11 @tC0
514 vdup.8 d11, r2 @D11 = alpha
522 vclt.u8 d4, d4, d11 @|p0-q0| < alpha ?
601 vdup.8 d11, r2 @D11 = alpha
606 vclt.u8 d4, d4, d11 @|p0-q0| < alpha ?
640 vqadd.u8 d11, d2, d7 @q0+|delta
[all...] |
| ih264_iquant_itrans_recon_a9.s | 189 vtrn.16 d10, d11
192 vtrn.32 d11, d13
197 vshr.s16 d18, d11, #1 @q0>>1
201 vadd.s16 d17, d11, d19 @x3 = q0+ (q1 >> 1);
364 vtrn.16 d10, d11
367 vtrn.32 d11, d13
372 vshr.s16 d18, d11, #1 @q0>>1
376 vadd.s16 d17, d11, d19 @x3 = q0+ (q1 >> 1);
570 vqrshrn.s32 d11, q7, #0x6 @ D11 = c[i] = ((q[i] + 32) >> 6) where i = 44..4
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCDuplexInfo.cpp | 681 case Hexagon::D11:
[all...] |
| HexagonMCInstrInfo.cpp | 385 (Reg >= Hexagon::D8 && Reg <= Hexagon::D11));
|
| /external/llvm/lib/Target/Sparc/Disassembler/ |
| SparcDisassembler.cpp | 93 SP::D10, SP::D26, SP::D11, SP::D27,
|
| /external/valgrind/memcheck/ |
| mc_machine.c | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 662 Hexagon::D10, Hexagon::D11, Hexagon::D12, Hexagon::D13,
[all...] |
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | [all...] |
| /external/llvm/lib/Target/Hexagon/Disassembler/ |
| HexagonDisassembler.cpp | 525 Hexagon::D8, Hexagon::D9, Hexagon::D10, Hexagon::D11,
[all...] |
| /external/llvm/lib/Target/AArch64/Disassembler/ |
| AArch64Disassembler.cpp | 287 AArch64::D10, AArch64::D11, AArch64::D12, AArch64::D13, AArch64::D14,
[all...] |
| /external/icu/icu4c/source/test/testdata/ |
| nfs4_cis_prep.txt | 157 0D11; ; UNASSIGNED
[all...] |
| nfs4_cs_prep_ci.txt | 157 0D11; ; UNASSIGNED
[all...] |
| nfs4_mixed_prep_s.txt | 157 0D11; ; UNASSIGNED
[all...] |
| /external/llvm/lib/Target/ARM/Disassembler/ |
| ARMDisassembler.cpp | [all...] |
