| /external/llvm/lib/Target/AArch64/ |
| AArch64RegisterInfo.cpp | 330 unsigned Shifter = AArch64_AM::getShifterImm(AArch64_AM::LSL, 0);
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_PredictReconCoefIntra_s.s | 148 ADD index,index,videoComp,LSL #5
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| armVCM4P10_InterpolateLuma_HalfDiagVerHor4x4_unsafe_s.s | 134 ADD r12, pSrc, srcStep, LSL #2
|
| armVCM4P10_Interpolate_Chroma_s.s | 179 LDR pc, [pTable, iWidth, LSL #1] ;// Branch to the case based on iWidth
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| /external/llvm/lib/Target/AArch64/AsmParser/ |
| AArch64AsmParser.cpp | 700 // An ADD/SUB shifter is either 'lsl #0' or 'lsl #12'.
738 // An ADD/SUB shifter is either 'lsl #0' or 'lsl #12'.
872 // "lsl #0" takes precedence: in practice this only affects "#0, lsl #0".
993 return (ST == AArch64_AM::LSL || ST == AArch64_AM::LSR ||
1006 ET == AArch64_AM::LSL) &&
1022 ET == AArch64_AM::LSL) &&
1030 return (ET == AArch64_AM::LSL || ET == AArch64_AM::SXTX) &
[all...] |
| /external/v8/src/arm/ |
| assembler-arm.h | 491 return Operand(key, LSL, kPointerSizeLog2 - kSmiTagSize);
495 return Operand(key, LSL, kDoubleSizeLog2 - kSmiTagSize);
563 return MemOperand(array, key, LSL, kPointerSizeLog2 - kSmiTagSize, am);
866 void lsl(Register dst, Register src1, const Operand& src2, SBit s = LeaveCC,
869 mov(dst, Operand(src1, LSL, src2.rm()), s, cond);
871 mov(dst, Operand(src1, LSL, src2.immediate()), s, cond);
928 // usat dst, #satpos, src, lsl #sh
[all...] |
| constants-arm.h | 257 LSL = 0 << 5, // Logical shift left.
|
| deoptimizer-arm.cc | 242 __ add(r1, r4, Operand(r1, LSL, 2));
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/metag/ |
| metafpu21.d | [all...] |
| metafpu21.s | [all...] |
| metacore12.d | [all...] |
| /art/compiler/optimizing/ |
| intrinsics_arm.cc | [all...] |
| intrinsics_arm64.cc | [all...] |
| code_generator_arm.cc | 513 // calls to art::arm::Thumb2Assembler::Lsl and
548 __ Lsl(index_reg, index_reg, TIMES_4);
[all...] |
| /external/vixl/src/vixl/a64/ |
| macro-assembler-a64.cc | 858 movi(vd, byte2, LSL, 8);
862 mvni(vd, ~byte2 & 0xff, LSL, 8);
899 movi(vd, bytes[i], LSL, i * 8);
908 mvni(vd, ~bytes[i] & 0xff, LSL, i * 8);
995 if (shift_amount != 0 || shift != LSL) {
[all...] |
| /external/v8/src/arm64/ |
| macro-assembler-arm64.cc | 461 return Operand(dst, LSL, shift_low);
[all...] |
| deoptimizer-arm64.cc | 221 __ Add(x1, x0, Operand(x1, LSL, kPointerSizeLog2));
|
| macro-assembler-arm64-inl.h | 901 void MacroAssembler::Lsl(const Register& rd,
906 lsl(rd, rn, shift);
910 void MacroAssembler::Lsl(const Register& rd,
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPS64Assembler.cpp | 386 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
509 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
536 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
[all...] |
| ARMAssemblerInterface.h | 43 LSL, LSR, ASR, ROR
|
| /external/libhevc/common/arm/ |
| ihevc_sao_band_offset_luma.s | 96 LSL r11,r5,#3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_PredictIntraChroma_8x8_s.S | 47 LDR r8,[r8,r6,LSL #2]
|
| omxVCM4P10_PredictIntra_16x16_s.S | 54 LDR r9,[r9,r6,LSL #2]
|
| omxVCM4P10_PredictIntra_4x4_s.S | 44 LDR r8,[r8,r6,LSL #2]
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| omxVCM4P2_PredictReconCoefIntra_s.s | 178 ADD index,index,videoComp,LSL #5
|
