| /external/libhevc/common/arm/ |
| ihevc_sao_band_offset_chroma.s | 103 LSL r6,r5,#3 @sao_band_pos_u
152 LSL r11,r6,#3 @sao_band_pos_v
|
| ihevc_sao_edge_offset_class0_chroma.s | 317 LSL r14,r14,#1 @(ht - row) * 2
401 LSL r14,r14,#1 @II (ht - row) * 2
|
| /external/libhevc/common/arm64/ |
| ihevc_sao_edge_offset_class0_chroma.s | 356 LSL x14,x14,#1 //(ht - row) * 2
447 LSL x14,x14,#1 //II (ht - row) * 2
|
| ihevc_sao_edge_offset_class3.s | 359 ADD x8,x0,x1,LSL #1 //II *pu1_src + src_strd
485 ADD x8,x0,x1,LSL #1 //*pu1_src + src_strd
[all...] |
| /external/llvm/test/MC/ARM/ |
| basic-thumb-instructions.s | 351 @ LSL (immediate)
367 @ LSL (register)
|
| thumb-diagnostics.s | 153 @ Out of range immediates for LSL instruction.
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| illegal.s | 68 strb x0, [sp, x1, lsl #0]
69 strb w7, [x30, x0, lsl]
70 strb w7, [x30, x0, lsl #1]
203 movz x1,#:abs_g2:u48, lsl #16
204 movz x1, 0xddee, lsl #8
214 bic v0.4s, #1, lsl #31
215 // bic v0.4h, #1, lsl #16
220 movi v0.4s, #127, lsl #4
222 // movi v0.4h, #127, lsl #16
224 mvni v0.4s, #127, lsl #
[all...] |
| /external/vixl/test/ |
| test-assembler-a64.cc | 292 __ Mvn(w2, Operand(w0, LSL, 1));
293 __ Mvn(x3, Operand(x1, LSL, 2));
465 __ Mov(w13, Operand(w11, LSL, 1));
466 __ Mov(x14, Operand(x12, LSL, 2));
524 __ Orr(w3, w0, Operand(w1, LSL, 28));
525 __ Orr(x4, x0, Operand(x1, LSL, 32));
618 __ Orn(w3, w0, Operand(w1, LSL, 4));
619 __ Orn(x4, x0, Operand(x1, LSL, 4));
685 __ And(w3, w0, Operand(w1, LSL, 4));
686 __ And(x4, x0, Operand(x1, LSL, 4))
[all...] |
| /external/v8/test/cctest/ |
| test-assembler-arm64.cc | 302 __ Mvn(w2, Operand(w0, LSL, 1));
303 __ Mvn(x3, Operand(x1, LSL, 2));
375 __ Mov(w13, Operand(w11, LSL, 1));
376 __ Mov(x14, Operand(x12, LSL, 2));
532 __ Orr(w3, w0, Operand(w1, LSL, 28));
533 __ Orr(x4, x0, Operand(x1, LSL, 32));
629 __ Orn(w3, w0, Operand(w1, LSL, 4));
630 __ Orn(x4, x0, Operand(x1, LSL, 4));
698 __ And(w3, w0, Operand(w1, LSL, 4));
699 __ And(x4, x0, Operand(x1, LSL, 4))
[all...] |
| /art/compiler/utils/ |
| assembler_thumb_test.cc | 437 __ movs(R3, ShifterOperand(R4, LSL, 4));
448 __ mov(R3, ShifterOperand(R4, LSL, 4), AL, kCcKeep);
455 __ movs(R8, ShifterOperand(R4, LSL, 4));
469 __ Lsl(R3, R4, 4);
480 __ Lsl(R3, R4, 4, AL, kCcKeep);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64InstrInfo.cpp | [all...] |
| AArch64FastISel.cpp | 666 Addr.setExtendType(AArch64_AM::LSL);
750 Addr.setExtendType(AArch64_AM::LSL);
795 Addr.setExtendType(AArch64_AM::LSL);
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.h | 273 am_(am), is_immed_offset_(true), shift_(LSL) {
277 am_(am), is_immed_offset_(false), shift_(LSL) {
290 am_(Offset), is_immed_offset_(false), shift_(LSL) {
819 virtual void Lsl(Register rd, Register rm, uint32_t shift_imm,
823 Lsl(rd, rm, shift_imm, cond, kCcSet);
854 virtual void Lsl(Register rd, Register rm, Register rn,
858 Lsl(rd, rm, rn, cond, kCcSet);
[all...] |
| assembler_arm.cc | 147 (immed_ == 0u && shift_ == LSL) ||
227 // Only Offset mode is supported. Shift must be LSL and the count
229 CHECK_EQ(shift_, LSL);
[all...] |
| assembler_arm32_test.cc | 170 arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR, arm::Shift::ROR, arm::Shift::RRX
205 static constexpr arm::Shift kShifts[] = { arm::Shift::LSL, arm::Shift::LSR, arm::Shift::ASR,
|
| /external/v8/src/regexp/arm64/ |
| regexp-macro-assembler-arm64.cc | 270 backtrack_stackpointer(), Operand(x11, LSL, kWRegSizeLog2));
808 Operand(start_offset(), LSL, (mode_ == UC16) ? 1 : 0));
812 Operand(string_start_minus_one().X(), LSL, kWRegSizeInBits));
[all...] |
| /system/core/libpixelflinger/codeflinger/ |
| MIPSAssembler.cpp | 397 case LSL: mMips->SLL(tmpReg, amode.reg, amode.value); break;
508 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
540 case LSL: mMips->SLL(Rd, amode.reg, amode.value); break;
[all...] |
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64MCCodeEmitter.cpp | 268 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL &&
|
| /external/v8/src/compiler/arm/ |
| code-generator-arm.cc | 80 return Operand(InputRegister(index + 0), LSL, InputInt5(index + 1));
82 return Operand(InputRegister(index + 0), LSL, InputRegister(index + 1));
113 LSL, InputInt32(index + 2));
[all...] |
| /external/valgrind/exp-bbv/tests/arm-linux/ |
| ll.S | 59 orr r5,r4,r5,LSL #8 @ shift 0xff left by 8 and or in the byte we loaded
73 orr r4,r0,r4,LSL #8 @ merge back into 16 bits
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| omxVCM4P10_PredictIntraChroma_8x8_s.s | 199 LDR pc, [pTable, predMode, LSL #2] ;// Branch to the case based on preMode
|
| omxVCM4P10_PredictIntra_16x16_s.s | 203 LDR pc, [pTable, predMode, LSL #2] ;// Branch to the case based on preMode
|
| omxVCM4P10_PredictIntra_4x4_s.s | 187 LDR pc, [pTable, predMode, LSL #2] ;// Branch to the case based on preMode
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_ColorMatrix.S | [all...] |
| /external/libavc/common/arm/ |
| ih264_resi_trans_quant_a9.s | 113 sub r7, r11, r7 @Negate the qbit value for usiing LSL
308 sub r7, r11, r7 @Negate the qbit value for usiing LSL
|
