| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/api/ |
| armCOMM_IDCT_s.h | 251 PKHBT xi4, xi3, xi4, LSL #(16-SHIFT)
256 PKHBT xi5, xi0, xi5, LSL #(16-SHIFT)
260 PKHBT xi6, xi1, xi6, LSL #(16-SHIFT)
262 PKHBT xi7, xi2, xi7, LSL #(16-SHIFT)
276 PKHBT xi4, xi0, xi1, LSL #(16-SHIFT)
278 PKHBT xi5, xi2, xi3, LSL #(16-SHIFT)
288 PKHBT xi6, xi0, xi1, LSL #(16-SHIFT)
290 PKHBT xi7, xi2, xi3, LSL #(16-SHIFT)
322 PKHBT xi0, xi7, xi0, LSL #(16-SHIFT)
327 PKHBT xi1, xi4, xi1, LSL #(16-SHIFT
[all...] |
| /external/tremolo/Tremolo/ |
| bitwiseARM.s | 60 ORRLT r10,r10,r11,LSL r14 @ r10= Next 32 bits.
62 RSB r14,r14,r14,LSL r1
82 ORRLT r10,r10,r6,LSL r12 @ r10= first bitsLeftInSeg bits+crap
83 RSB r11,r11,r11,LSL r5 @ r11= mask
108 ORR r10,r10,r12,LSL r5 @ r10= first r5+8 bits
114 RSB r14,r14,r14,LSL r1
123 RSB r14,r14,r14,LSL r1
150 MOV r14,r14,LSL #3 @ r14= length in bits
194 MOV r10,r10,LSL #3 @ r10= bits to backtrk to word align
200 ADDS r2,r2,r12,LSL #3 @ r2 = length in bits after advanc
[all...] |
| dpen.s | 100 ADC r2, r6, r7, LSL #1 @ r8 = &t[chase*2+C]
146 ORR r0, r14,r10,LSL #8 @ r7 = chase = (next<<8) | r14
157 ADC r2, r6, r7, LSL #1 @ r8 = &t[chase*2+C]
183 MOV r8, r8, LSL #1 @ r8 = (chase+bit)<<1
197 MOV r7, r7, LSL #1
206 ORR r0, r14,r10,LSL #16 @ r7 = chase = (next<<16) | r14
216 LDR r7, [r6, r2, LSL #2]
266 MOVLT r14,r14,LSL r11 @ r14= add = s->q_min << -add (if add < 0)
271 MOVLT r12,r12,LSL r5 @ r12=mul<<-shiftM
273 MOVGT r14,r14,LSL r5 @ add <<= shift
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV5E/ |
| syn_filt_opt.s | 96 ORR r10, r6, r7, LSL #16 @ -a[2] -- -a[1]
97 ORR r12, r9, r11, LSL #16 @ -a[4] -- -a[3]
107 ORR r10, r6, r7, LSL #16 @ -a[6] -- -a[5]
108 ORR r12, r9, r11, LSL #16 @ -a[8] -- -a[7]
118 ORR r10, r6, r7, LSL #16 @ -a[10] -- -a[9]
119 ORR r12, r9, r11, LSL #16 @ -a[12] -- -a[11]
129 ORR r10, r6, r7, LSL #16 @ -a[14] -- -a[13]
130 ORR r12, r9, r11, LSL #16 @ -a[16] -- -a[15]
137 ADD r10, r4, r8, LSL #1 @ temp_p = yy + i
215 MOV r7, r14, LSL #4 @ L_tmp <<=
[all...] |
| residu_asm_opt.s | 37 ORR r5, r6, r5, LSL #16 @r5 --- a0, a1
41 ORR r6, r7, r6, LSL #16 @r6 --- a2, a3
45 ORR r7, r8, r7, LSL #16 @r7 --- a4, a5
49 ORR r8, r9, r8, LSL #16 @r8 --- a6, a7
53 ORR r9, r10, r9, LSL #16 @r9 --- a8, a9
57 ORR r10, r11, r10, LSL #16 @r10 --- a10, a11
61 ORR r11, r12, r11, LSL #16 @r11 --- a12, a13
65 ORR r12, r4, r12, LSL #16 @r12 --- a14, a15
73 ORR r14, r4, r14, LSL #16 @r14 --- loopnum, a16
|
| pred_lt4_1_opt.s | 42 ADD r5, r0, r4, LSL #1 @x = exc - T0
52 MOV r8, r4, LSL #6
244 @SSAT r10, #32, r10, LSL #2
245 @SSAT r11, #32, r11, LSL #2
246 @SSAT r12, #32, r12, LSL #2
248 MOV r10, r10, LSL #1
249 MOV r11, r11, LSL #1
250 MOV r12, r12, LSL #1
436 @SSAT r10, #32, r10, LSL #2
437 @SSAT r11, #32, r11, LSL #
[all...] |
| /frameworks/av/media/libstagefright/codecs/amrwbenc/src/asm/ARMV7/ |
| Norm_Corr_neon.s | 59 ADD r5, r0, r11, LSL #1 @get the &exc[k]
169 ADD r5, r10, r5, LSL #1 @L_tmp = (L_tmp << 1) + 1
170 ADD r6, r10, r6, LSL #1 @L_tmp1 = (L_tmp1 << 1) + 1
178 MOV r5, r5, LSL r10 @L_tmp = (L_tmp << exp)
184 MOV r6, r6, LSL r5 @L_tmp = (L_tmp1 << exp)
218 MOVGT r12, r12, LSL r6 @L_tmp = L_shl(L_tmp, exp_corr + exp_norm + scale)
225 ADD r10, r5, r4, LSL #1 @ get corr_norm[t] address
239 ADD r8, r8, r5, LSL #1 @ exc[k] address
240 ADD r9, r9, r6, LSL #1 @ h[i] address
241 ADD r10, r10, r6, LSL #1 @ excf[i] addres
[all...] |
| pred_lt4_1_neon.s | 37 SUB r4, r0, r1, LSL #1 @ x = exc - T0
49 ADD r11, r11, r2, LSL #6 @ get inter4_2[k][]
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm11_asm/ |
| h264bsd_interpolate_hor_quarter.s | 149 ADD tmp2, partH, partW, LSL #4
150 ADD count, count, tmp2, LSL #16
158 ADD count, count, tmp1, LSL #8
161 ADD count, count, tmp3, LSL #8
194 PKHBT tmp2, tmp2, tmp4, LSL #(16-5)
195 PKHBT tmp1, tmp1, tmp3, LSL #(16-5)
203 ORR tmp1, tmp1, tmp2, LSL #8
240 PKHBT tmp2, tmp2, tmp4, LSL #(16-5)
241 PKHBT tmp1, tmp1, tmp3, LSL #(16-5)
249 ORR tmp1, tmp1, tmp2, LSL #
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src/ |
| omxVCM4P10_FilterDeblockingLuma_HorEdge_I_s.s | 176 SUB pSrcDst, pSrcDst, srcdstStep, LSL #2
240 SUB pSrcDst, pSrcDst, srcdstStep, LSL #2
248 SUB pTmp, pSrcDst, srcdstStep, LSL #2
265 SUB pSrcDst, pSrcDst, srcdstStep, LSL #2
266 SUB pSrcDst, pSrcDst, srcdstStep, LSL #1
273 SUB pTmp, pSrcDst, srcdstStep, LSL #2
287 ADD pSrcDst, pSrcDst, srcdstStep, LSL #2
|
| armVCM4P10_DecodeCoeffsToPair_s.s | 131 LDR pVLDTable, [pVLDTable, nC, LSL #2] ;// Find VLD table
161 SUB T1, T1, Symbol, LSL #1
198 MOV Symbol, Symbol, LSL SuffixLength
233 LDR pVLDTable, [pVLDTable, TotalCoeff, LSL #2]
250 LDR pVLDTable, [ppRunTable, ZerosLeft, LSL#2]
|
| omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.s | 114 SUB pSrcDst, pSrcDst, srcdstStep, LSL #1 ;?
176 SUB pSrcDst, pSrcDst, srcdstStep, LSL #2
202 SUB pSrcDst, pSrcDst, srcdstStep, LSL #1
|
| /frameworks/rs/cpu_ref/ |
| rsCpuIntrinsics_advsimd_Resize.S | 113 lsl x2, x0, #VECSHIFT
118 add x0, x0, x1, LSL #32
184 lsl x9, x3, #VECSHIFT
208 sub x14, x12, x13, LSL #(COMPONENT_SHIFT + 1)
241 sub x4, x4, x13, LSL #(COMPONENT_SHIFT)
242 sub x5, x5, x13, LSL #(COMPONENT_SHIFT)
243 sub x6, x6, x13, LSL #(COMPONENT_SHIFT)
244 sub x7, x7, x13, LSL #(COMPONENT_SHIFT)
254 lsl x2, x2, #(47 - CHUNKSHIFT)
255 lsl x3, x3, #(47 - CHUNKSHIFT
[all...] |
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p10/src_gcc/ |
| omxVCM4P10_FilterDeblockingChroma_HorEdge_I_s.S | 33 SUB r0,r0,r1,LSL #1
74 SUB r0,r0,r1,LSL #2
90 SUB r0,r0,r1,LSL #1
|
| omxVCM4P10_FilterDeblockingLuma_VerEdge_I_s.S | 62 SUB r0,r0,r1,LSL #3
113 SUB r0,r0,r1,LSL #3
152 SUB r0,r0,r1,LSL #3
162 ADD r0,r0,r1,LSL #3
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/arm/ |
| sp-pc-validations-bad-t.l | 16 [^:]*:45: Error: branch must be last instruction in IT block -- `ldreq.w r15,\[r0,r1,LSL#2\]'
32 [^:]*:69: Error: r15 not allowed here -- `ldrb.w pc,\[r0,r1,LSL#1\]'
34 [^:]*:71: Error: r15 not allowed here -- `ldrb.w r2,\[r0,pc,LSL#2\]'
35 [^:]*:72: Error: r13 not allowed here -- `ldrb.w r2,\[r0,sp,LSL#2\]'
96 [^:]*:152: Error: r15 not allowed here -- `ldrh.w pc,\[r0,r1,LSL#1\]'
97 [^:]*:153: Error: r13 not allowed here -- `ldrh.w sp,\[r0,r1,LSL#1\]'
98 [^:]*:154: Error: r15 not allowed here -- `ldrh.w r2,\[r0,pc,LSL#1\]'
99 [^:]*:155: Error: r13 not allowed here -- `ldrh.w r2,\[r0,sp,LSL#1\]'
117 [^:]*:182: Error: r15 not allowed here -- `ldrsb.w pc,\[r0,r1,LSL#2\]'
118 [^:]*:184: Error: r13 not allowed here -- `ldrsb.w sp,\[r0,r1,LSL#2\]
[all...] |
| archv6.s | 13 pkhbt r2, r5, r8, LSL #3
14 pkhbtal r2, r5, r8, LSL #3
15 pkhbteq r2, r5, r8, LSL #3
122 ssat r1, #1, r2, LSL #2
195 usat r1, #15, r2, LSL #4
200 usatle r1, #15, r2, LSL #4
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p2/src/ |
| omxVCM4P2_DecodeVLCZigzag_IntraACVLC_s.s | 126 ADD pZigzagTable, pZigzagTable, PredDir, LSL #6 ;// Loading Different type of zigzag tables based on PredDir
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm_neon/vc/m4p2/src/ |
| omxVCM4P2_DecodeVLCZigzag_IntraACVLC_s.s | 126 ADD pZigzagTable, pZigzagTable, PredDir, LSL #6 ;// Loading Different type of zigzag tables based on PredDir
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/omxdl/arm11/vc/m4p10/src/ |
| armVCM4P10_DecodeCoeffsToPair_s.s | 131 LDR pVLDTable, [pVLDTable, nC, LSL #2] ;// Find VLD table
161 SUB T1, T1, Symbol, LSL #1
198 MOV Symbol, Symbol, LSL SuffixLength
233 LDR pVLDTable, [pVLDTable, TotalCoeff, LSL #2]
250 LDR pVLDTable, [ppRunTable, ZerosLeft, LSL#2]
|
| armVCM4P10_DeblockingLuma_unsafe_s.s | 198 EOR u1, u1, m01 ,LSL #7
252 ADD alpha, alpha, m01, LSL #1
306 EOR a, a, m01, LSL #7
354 EOR t10, t10, m01, LSL #7
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm/ |
| h264bsdFlushBits.s | 65 CMP readBits, strmBuffSize, LSL #3
|
| /frameworks/av/media/libstagefright/codecs/on2/h264dec/source/arm_neon_asm_gcc/ |
| h264bsdFlushBits.S | 63 CMP readBits, strmBuffSize, LSL #3
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/aarch64/ |
| addsub.s | 29 // or implicitly UXTX, SXTX or LSL; otherwise it Wm.
33 .ifnc \extend, LSL
107 // when <extend> is LSL, <amount> cannot be absent
110 do_addsub_ext \type, \op, \Rn, \reg, LSL, \amount
160 .irp shift, LSL, LSR, ASR
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/epiphany/ |
| regression.s | 29 LSL R0,R0,#2 ; //Create 00020000
172 LSLLAB: LSL R63,R3,#0x2 ; //3<<2=12
177 LSLILAB: LSL R63,R3,R2 ; //3<<2=12
|
