| /external/mesa3d/src/mesa/drivers/dri/i965/ |
| gen7_misc_state.c | 196 ((ctx->Depth.Mask != 0) << 28) |
|
| /external/mesa3d/src/mesa/drivers/dri/nouveau/ |
| nouveau_driver.c | 107 unsigned mask, value; local
117 mask = pack_rgba_i(s->format, ctx->Color.ColorMask[0]);
120 if (mask)
122 ctx, s, mask, value, x, y, w, h);
127 mask = pack_zs_i(s->format,
129 ctx->Depth.Mask) ? ~0 : 0,
136 if (mask)
138 ctx, s, mask, value, x, y, w, h);
|
| nv04_state_raster.c | 150 if (ctx->Depth.Mask)
162 /* Color mask. */
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_atom_depth.c | 107 dsa->depth.writemask = ctx->Depth.Mask;
|
| /external/llvm/include/llvm/Analysis/ |
| TargetFolder.h | 253 Constant *Mask) const {
254 return Fold(ConstantExpr::getShuffleVector(V1, V2, Mask));
|
| /external/llvm/include/llvm/IR/ |
| ConstantFolder.h | 228 Constant *Mask) const {
229 return ConstantExpr::getShuffleVector(V1, V2, Mask);
|
| NoFolder.h | 282 Constant *Mask) const {
283 return new ShuffleVectorInst(V1, V2, Mask);
|
| /external/llvm/lib/CodeGen/ |
| CodeGenPrepare.cpp | 68 "Number of and mask instructions added to form ext loads");
69 STATISTIC(NumAndUses, "Number of uses of and mask instructions optimized");
241 // If there is a mask, compare against zero, and branch that can be combined
242 // into a single target instruction, push the mask and compare into branch
[all...] |
| RegisterCoalescer.cpp | 796 LaneBitmask Mask = MRI->getMaxLaneMaskForVReg(IntA.reg);
797 IntA.createSubRangeFrom(Allocator, Mask, IntA);
[all...] |
| StackMaps.cpp | 237 /// Parse the register live-out mask and return a vector of live-out registers
240 StackMaps::parseRegisterLiveOutMask(const uint32_t *Mask) const {
241 assert(Mask && "No register mask specified");
245 // Create a LiveOutReg for each bit that is set in the register mask.
247 if ((Mask[Reg / 32] >> Reg % 32) & 1)
|
| /external/pdfium/core/ |
| pdfiumfxge.mk | 14 # Mask some warnings. These are benign, but we probably want to fix them
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2InstrInfo.cpp | 80 unsigned Mask = MBBI->getOperand(1).getImm();
86 MBBI->getOperand(1).setImm((Mask & MaskOff) | MaskOn);
593 unsigned Mask = (1 << NumBits) - 1;
594 if ((unsigned)Offset <= Mask * Scale) {
610 ImmedOffset = ImmedOffset & Mask;
623 Offset &= ~(Mask*Scale);
|
| /external/llvm/lib/Transforms/InstCombine/ |
| InstCombineAndOrXor.cpp | 41 /// a three bit mask. It also returns whether it is an ordered predicate by
190 // NOTE: This reduces the number of bits set in the & mask, which
359 /// This is part of an expression (LHS +/- RHS) & Mask, where isSub determines
362 /// ((A & N) +/- B) & Mask -> (A +/- B) & Mask iff N&Mask == Mask
363 /// ((A | N) +/- B) & Mask -> (A +/- B) & Mask iff N&Mask ==
707 unsigned mask = foldLogOpOfMaskedICmpsHelper(A, B, C, D, E, LHS, RHS, local
[all...] |
| /external/pdfium/core/src/fxge/ge/ |
| fx_ge_path.cpp | 44 CFX_DIBitmapRef Mask) {
45 const CFX_DIBitmap* mask_dib = Mask;
54 m_Mask = Mask;
72 void CFX_ClipRgn::IntersectMaskF(int left, int top, CFX_DIBitmapRef Mask) {
73 const CFX_DIBitmap* mask_dib = Mask;
78 IntersectMaskRect(m_Box, mask_box, Mask);
|
| /external/llvm/lib/IR/ |
| Instructions.cpp | [all...] |
| /external/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | [all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64FastISel.cpp | [all...] |
| /prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/ |
| winnt.h | [all...] |
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAGBuilder.h | 198 uint64_t Mask;
203 CaseBits(uint64_t mask, MachineBasicBlock* bb, unsigned bits,
205 Mask(mask), BB(bb), Bits(bits), ExtraProb(Prob) { }
207 CaseBits() : Mask(0), BB(nullptr), Bits(0) {}
276 Mask(M), ThisBB(T), TargetBB(Tr), ExtraProb(Prob) { }
277 uint64_t Mask;
[all...] |
| DAGCombiner.cpp | 375 SDValue GetDemandedBits(SDValue V, const APInt &Mask);
[all...] |
| /external/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 56 // The mask of CC values that Opcode can produce.
59 // The mask of CC values for which the original condition is true.
[all...] |
| /external/llvm/include/llvm/Support/ |
| MathExtras.h | 53 T Mask = std::numeric_limits<T>::max() >> Shift;
55 if ((Val & Mask) == 0) {
60 Mask >>= Shift;
|
| /external/llvm/tools/llvm-readobj/ |
| ARMEHABIPrinter.h | 33 uint8_t Mask;
63 void PrintRegisters(uint32_t Mask, StringRef Prefix);
295 if ((Opcodes[OCI ^ 3] & Ring[REI].Mask) == Ring[REI].Value) {
|
| /external/libnfc-nxp/src/ |
| phFriNfc_NdefRecord.c | 381 static uint8_t phFriNfc_NdefRecord_NdefFlag(uint8_t Flags,uint8_t Mask)
384 check_flag = Flags & Mask;
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| MachineInstrBuilder.h | 149 const MachineInstrBuilder &addRegMask(const uint32_t *Mask) const {
150 MI->addOperand(*MF, MachineOperand::CreateRegMask(Mask));
|
