| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | 108 unsigned Op0, bool Op0IsKill);
111 unsigned Op0, bool Op0IsKill,
115 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill,
124 unsigned Op0, bool Op0IsKill,
286 unsigned Op0, bool Op0IsKill) {
292 Op0 = constrainOperandRegClass(II, Op0, 1);
295 ResultReg).addReg(Op0, Op0IsKill * RegState::Kill));
298 .addReg(Op0, Op0IsKill * RegState::Kill))
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonPeephole.cpp | 247 MachineOperand &Op0 = MI->getOperand(0);
248 unsigned Reg0 = Op0.getReg();
251 // Handle instructions that have a prediate register in op0
|
| HexagonCopyToCombine.cpp | 120 const MachineOperand &Op0 = MI->getOperand(0);
122 assert(Op0.isReg() && Op1.isReg());
124 unsigned DestReg = Op0.getReg();
133 const MachineOperand &Op0 = MI->getOperand(0);
135 assert(Op0.isReg());
137 unsigned DestReg = Op0.getReg();
|
| HexagonGenPredicate.cpp | 396 MachineOperand &Op0 = MI->getOperand(0);
397 assert(Op0.isDef());
398 Register OutR(Op0);
|
| /external/llvm/include/llvm/IR/ |
| PatternMatch.h | [all...] |
| /external/llvm/lib/Target/AArch64/Utils/ |
| AArch64BaseInfo.cpp | 858 // Try to parse an S<op0>_<op1>_<Cn>_<Cm>_<op2> register name
867 uint32_t Op0 = 0, Op1 = 0, CRn = 0, CRm = 0, Op2 = 0;
869 Ops[1].getAsInteger(10, Op0);
874 Bits = (Op0 << 14) | (Op1 << 11) | (CRn << 7) | (CRm << 3) | Op2;
899 uint32_t Op0 = (Bits >> 14) & 0x3;
905 return "s" + utostr(Op0)+ "_" + utostr(Op1) + "_c" + utostr(CRn)
|
| /external/llvm/lib/Target/AArch64/InstPrinter/ |
| AArch64InstPrinter.cpp | 66 const MCOperand &Op0 = MI->getOperand(0);
99 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
135 O << '\t' << AsmMnemonic << '\t' << getRegisterName(Op0.getReg())
145 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
153 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op1.getReg())
160 const MCOperand &Op0 = MI->getOperand(0); // Op1 == Op0
172 O << "\tbfc\t" << getRegisterName(Op0.getReg())
182 O << "\tbfi\t" << getRegisterName(Op0.getReg()) << ", "
192 << getRegisterName(Op0.getReg()) << ", " << getRegisterName(Op2.getReg()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEISelLowering.cpp | 554 SDValue Op0 = N->getOperand(0);
556 unsigned Op0Opcode = Op0->getOpcode();
574 SDValue Op0Op2 = Op0->getOperand(2);
581 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 };
582 return DAG.getNode(MipsISD::VEXTRACT_ZEXT_ELT, SDLoc(Op0),
583 Op0->getVTList(),
584 makeArrayRef(Ops, Op0->getNumOperands()));
674 SDValue Op0 = N->getOperand(0);
677 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND)
[all...] |
| MipsFastISel.cpp | 167 unsigned Op0, bool Op0IsKill,
174 unsigned Op0, bool Op0IsKill, uint64_t imm1,
867 Value *Op0 = I->getOperand(0);
880 SrcReg = getRegForValue(Op0);
[all...] |
| /external/llvm/include/llvm/Analysis/ |
| InstructionSimplify.h | 154 Value *SimplifyShlInst(Value *Op0, Value *Op1, bool isNSW, bool isNUW,
163 Value *SimplifyLShrInst(Value *Op0, Value *Op1, bool isExact,
172 Value *SimplifyAShrInst(Value *Op0, Value *Op1, bool isExact,
|
| ScalarEvolution.h | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelDAGToDAG.cpp | 286 SDValue Op0, Op1;
290 if (!SelectAddr(Op, Op0, Op1))
295 OutOps.push_back(Op0);
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/detail/ |
| reduce.hpp | 168 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
173 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
178 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
182 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/block/detail/ |
| reduce.hpp | 186 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
191 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
207 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
211 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | [all...] |
| LegalizeDAG.cpp | [all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFastISel.cpp | 116 unsigned Op0, bool Op0IsKill,
120 unsigned Op0, bool Op0IsKill);
123 unsigned Op0, bool Op0IsKill,
720 Value *Op0 = I->getOperand(0);
729 if (!isLoadTypeLegal(Op0->getType(), VT))
733 SrcReg = getRegForValue(Op0);
[all...] |
| PPCISelDAGToDAG.cpp | 520 SDValue Op0 = N->getOperand(0);
525 CurDAG->computeKnownBits(Op0, LKZ, LKO);
532 unsigned Op0Opc = Op0.getOpcode();
541 if (Op0.getOperand(0).getOpcode() == ISD::SHL ||
542 Op0.getOperand(0).getOpcode() == ISD::SRL) {
545 std::swap(Op0, Op1);
553 std::swap(Op0, Op1);
587 SDValue Ops[] = { Op0, Op1, getI32Imm(SH, dl), getI32Imm(MB, dl),
[all...] |
| /external/llvm/lib/ExecutionEngine/Interpreter/ |
| Execution.cpp | [all...] |
| /external/llvm/lib/CodeGen/ |
| IntrinsicLowering.cpp | 496 Value *Op0 = CI->getArgOperand(0);
497 Type *IntPtr = DL.getIntPtrType(Op0->getType());
501 Ops[0] = Op0;
|
| /external/opencv3/modules/core/include/opencv2/core/cuda/ |
| reduce.hpp | 66 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
70 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
75 const thrust::tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
|
| /external/opencv3/modules/cudev/include/opencv2/cudev/warp/ |
| reduce.hpp | 69 class Op0, class Op1, class Op2, class Op3, class Op4, class Op5, class Op6, class Op7, class Op8, class Op9>
73 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>& op)
78 const tuple<Op0, Op1, Op2, Op3, Op4, Op5, Op6, Op7, Op8, Op9>&>(smem, val, tid, op);
|
| /external/llvm/include/llvm/CodeGen/ |
| SelectionDAGNodes.h | 809 void InitOperands(SDUse *Ops, const SDValue &Op0) {
811 Ops[0].setInitial(Op0);
818 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1) {
820 Ops[0].setInitial(Op0);
829 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1,
832 Ops[0].setInitial(Op0);
843 void InitOperands(SDUse *Ops, const SDValue &Op0, const SDValue &Op1,
846 Ops[0].setInitial(Op0);
[all...] |
| /external/llvm/lib/Target/AArch64/ |
| AArch64LoadStoreOptimizer.cpp | 556 // Copy MachineMemOperands from Op0 and Op1 to a new array assigned to MI.
557 static void concatenateMemOperands(MachineInstr *MI, MachineInstr *Op0,
560 size_t numMemRefs = (Op0->memoperands_end() - Op0->memoperands_begin()) +
566 std::copy(Op0->memoperands_begin(), Op0->memoperands_end(), MemBegin);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86ISelLowering.cpp | [all...] |
