| /external/mesa3d/src/mesa/program/ |
| prog_instruction.c | 144 gl_inst_opcode Opcode;
152 * \note Opcode should equal array index!
254 * Return the number of src registers for the given instruction/opcode.
257 _mesa_num_inst_src_regs(gl_inst_opcode opcode)
259 ASSERT(opcode < MAX_OPCODE);
260 ASSERT(opcode == InstInfo[opcode].Opcode);
261 ASSERT(OPCODE_XPD == InstInfo[OPCODE_XPD].Opcode);
262 return InstInfo[opcode].NumSrcRegs
[all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMTargetTransformInfo.cpp | 50 int ARMTTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
51 int ISD = TLI->InstructionOpcodeToISD(Opcode);
52 assert(ISD && "Invalid opcode");
73 return BaseT::getCastInstrCost(Opcode, Dst, Src);
240 return BaseT::getCastInstrCost(Opcode, Dst, Src);
243 int ARMTTIImpl::getVectorInstrCost(unsigned Opcode, Type *ValTy,
248 Opcode == Instruction::InsertElement &&
253 if ((Opcode == Instruction::InsertElement ||
254 Opcode == Instruction::ExtractElement)) {
264 return std::max(BaseT::getVectorInstrCost(Opcode, ValTy, Index), 2U)
[all...] |
| ThumbRegisterInfo.cpp | 338 /// convertToNonSPOpcode - Change the opcode to the non-SP version, because
340 static unsigned convertToNonSPOpcode(unsigned Opcode) {
341 switch (Opcode) {
349 return Opcode;
362 unsigned Opcode = MI.getOpcode();
366 if (Opcode == ARM::tADDframe) {
398 unsigned NewOpc = convertToNonSPOpcode(Opcode);
399 if (NewOpc != Opcode && FrameReg != ARM::SP)
410 if (Opcode == ARM::tLDRspi || Opcode == ARM::tSTRspi)
[all...] |
| /external/javassist/src/main/javassist/expr/ |
| NewExpr.java | 142 if (op == Opcode.DUP)
144 else if (op == Opcode.DUP_X1
145 && iterator.byteAt(newPos + 4) == Opcode.SWAP)
|
| /external/llvm/lib/Target/BPF/MCTargetDesc/ |
| BPFMCCodeEmitter.cpp | 110 unsigned Opcode = MI.getOpcode();
114 if (Opcode == BPF::LD_imm64 || Opcode == BPF::LD_pseudo) {
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZRegisterInfo.cpp | 85 unsigned Opcode = MI->getOpcode();
86 unsigned OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
96 OpcodeForOffset = TII->getOpcodeForOffset(Opcode, Offset);
|
| SystemZElimCompare.cpp | 178 unsigned Opcode = MI->getOpcode();
180 if (Opcode == SystemZ::AHI)
182 else if (Opcode == SystemZ::AGHI)
224 unsigned Opcode = TII->getLoadAndTest(MI->getOpcode());
225 if (!Opcode)
228 MI->setDesc(TII->get(Opcode));
242 int Opcode = MI->getOpcode();
243 const MCInstrDesc &Desc = TII->get(Opcode);
|
| /external/mesa3d/src/gallium/drivers/r300/compiler/ |
| radeon_dataflow_swizzles.c | 54 mov->U.I.Opcode = RC_OPCODE_MOV;
95 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
98 for(src = 0; src < opcode->NumSrcRegs; ++src) {
99 if (!c->SwizzleCaps->IsNative(inst->U.I.Opcode, inst->U.I.SrcReg[src]))
|
| radeon_pair_schedule.c | 255 else if (sinst->Instruction->U.P.Alpha.Opcode == RC_OPCODE_NOP)
257 else if (sinst->Instruction->U.P.RGB.Opcode == RC_OPCODE_NOP)
456 inst_begin->U.I.Opcode = RC_OPCODE_BEGIN_TEX;
511 assert(dst_full->Alpha.Opcode == RC_OPCODE_NOP);
529 info = rc_get_opcode_info(dst_full->RGB.Opcode);
602 const struct rc_opcode_info * opcode; local
604 assert(rgb->Alpha.Opcode == RC_OPCODE_NOP);
605 assert(alpha->RGB.Opcode == RC_OPCODE_NOP);
625 opcode = rc_get_opcode_info(alpha->Alpha.Opcode);
1316 const struct rc_opcode_info * opcode = rc_get_opcode_info(inst->U.I.Opcode); local
[all...] |
| /external/smali/dexlib2/src/test/java/org/jf/dexlib2/ |
| AccessorTest.java | 114 Opcode opcode = instruction.getOpcode(); local
115 if (opcode == Opcode.INVOKE_STATIC || opcode == Opcode.INVOKE_STATIC_RANGE) {
|
| /art/compiler/dex/ |
| dex_to_dex_compiler.cc | 121 switch (inst->Opcode()) {
202 DCHECK_EQ(inst->Opcode(), Instruction::RETURN_VOID);
212 VLOG(compiler) << "Replacing " << Instruction::Name(inst->Opcode())
232 VLOG(compiler) << "Removing " << Instruction::Name(inst->Opcode())
260 VLOG(compiler) << "Quickening " << Instruction::Name(inst->Opcode())
295 VLOG(compiler) << "Quickening " << Instruction::Name(inst->Opcode())
|
| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_tgsi_info.c | 215 switch (inst->Instruction.Opcode) {
264 if (inst->Instruction.Opcode == TGSI_OPCODE_MOV) {
267 } else if (inst->Instruction.Opcode == TGSI_OPCODE_MUL) {
301 * Clear all temporaries information in presence of a control flow opcode.
304 switch (inst->Instruction.Opcode) {
428 if (inst->Instruction.Opcode == TGSI_OPCODE_END ||
429 inst->Instruction.Opcode == TGSI_OPCODE_BGNSUB) {
|
| /external/mesa3d/src/mesa/state_tracker/ |
| st_atom_pixeltransfer.c | 162 inst[ic].Opcode = OPCODE_TEX;
186 inst[ic].Opcode = OPCODE_MAD;
215 inst[ic].Opcode = OPCODE_TEX;
227 inst[ic].Opcode = OPCODE_TEX;
241 inst[ic].Opcode = OPCODE_MOV;
260 inst[ic].Opcode = OPCODE_END;
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 276 static int isSignedOp(ISD::CondCode Opcode) {
277 switch (Opcode) {
348 /// AddNodeIDOpcode - Add the node opcode to the NodeID data.
381 static void AddNodeIDFlags(FoldingSetNodeID &ID, unsigned Opcode,
383 if (!isBinOpWithFlags(Opcode))
687 // Set the opcode to DELETED_NODE to help catch bugs when node
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.cpp | 107 int Opcode = isImmU6(OpImm) ? XCore::EXTSP_u6 : XCore::EXTSP_lu6;
108 BuildMI(MBB, MBBI, dl, TII.get(Opcode)).addImm(OpImm);
129 int Opcode = isImmU6(OpImm) ? XCore::LDAWSP_ru6 : XCore::LDAWSP_lru6;
130 BuildMI(MBB, MBBI, dl, TII.get(Opcode), XCore::SP).addImm(OpImm);
200 int Opcode = isImmU6(Offset) ? XCore::LDWSP_ru6 : XCore::LDWSP_lru6;
201 BuildMI(MBB, MBBI, dl, TII.get(Opcode), SpillList[i].Reg)
261 int Opcode = isImmU6(Adjusted) ? XCore::ENTSP_u6 : XCore::ENTSP_lu6;
263 MachineInstrBuilder MIB = BuildMI(MBB, MBBI, dl, TII.get(Opcode));
286 int Opcode = isImmU6(Offset) ? XCore::STWSP_ru6 : XCore::STWSP_lru6;
288 BuildMI(MBB, MBBI, dl, TII.get(Opcode))
[all...] |
| /external/v8/src/mips/ |
| constants-mips.cc | 130 Opcode opcode = static_cast<Opcode>(instr & kOpcodeMask); local
131 switch (opcode) {
|
| /external/v8/src/mips64/ |
| constants-mips64.cc | 130 Opcode opcode = static_cast<Opcode>(instr & kOpcodeMask); local
131 switch (opcode) {
|
| /external/smali/smali/src/main/antlr/ |
| smaliTreeWalker.g | 672 "registers. Use the <op>/range alternate opcode instead.");
688 "registers. Use the <op>/range alternate opcode instead.");
782 Opcode opcode = opcodes.getOpcodeByName($INSTRUCTION_FORMAT10t.text);
783 $method::methodBuilder.addInstruction(new BuilderInstruction10t(opcode, $label_ref.label));
790 Opcode opcode = opcodes.getOpcodeByName($INSTRUCTION_FORMAT10x.text);
791 $method::methodBuilder.addInstruction(new BuilderInstruction10x(opcode));
798 Opcode opcode = opcodes.getOpcodeByName($INSTRUCTION_FORMAT11n.text)
[all...] |
| /external/llvm/lib/Transforms/Scalar/ |
| Reassociate.cpp | 225 /// Return true if V is an instruction of the specified opcode and if it
227 static BinaryOperator *isReassociableOp(Value *V, unsigned Opcode) {
229 cast<Instruction>(V)->getOpcode() == Opcode &&
385 static void IncorporateWeight(APInt &LHS, const APInt &RHS, unsigned Opcode) {
403 if (Instruction::isIdempotent(Opcode)) {
410 if (Instruction::isNilpotent(Opcode)) {
416 if (Opcode == Instruction::Add || Opcode == Instruction::FAdd) {
422 assert((Opcode == Instruction::Mul || Opcode == Instruction::FMul) &
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/builder/ |
| MutableMethodImplementation.java | 39 import org.jf.dexlib2.Opcode;
86 final Opcode opcode = instruction.getOpcode(); local
87 if (opcode == Opcode.PACKED_SWITCH_PAYLOAD || opcode == Opcode.SPARSE_SWITCH_PAYLOAD) {
350 if (instruction.getOpcode() != Opcode.NOP) {
374 if (targetInstruction.getOpcode() == Opcode.NOP) {
382 if ((instruction.opcode == Opcode.PACKED_SWITCH &
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86TargetTransformInfo.cpp | 89 unsigned Opcode, Type *Ty, TTI::OperandValueKind Op1Info,
95 int ISD = TLI->InstructionOpcodeToISD(Opcode);
96 assert(ISD && "Invalid opcode");
412 return BaseT::getArithmeticInstrCost(Opcode, Ty, Op1Info, Op2Info);
527 int X86TTIImpl::getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src) {
528 int ISD = TLI->InstructionOpcodeToISD(Opcode);
529 assert(ISD && "Invalid opcode");
[all...] |
| /external/smali/dexlib2/src/main/java/org/jf/dexlib2/analysis/ |
| MethodAnalyzer.java | 38 import org.jf.dexlib2.Opcode;
217 ex.addContext(String.format("opcode: %s", instructionToAnalyze.instruction.getOpcode().name));
443 Opcode instructionOpcode = instruction.instruction.getOpcode();
486 Opcode instructionOpcode = instruction.instruction.getOpcode();
501 if (instructionOpcode == Opcode.PACKED_SWITCH || instructionOpcode == Opcode.SPARSE_SWITCH) {
519 } else if (instructionOpcode != Opcode.FILL_ARRAY_DATA) {
541 if (!allowMoveException && successor.instruction.getOpcode() == Opcode.MOVE_EXCEPTION) {
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 96 SDNode *SelectIndexedLoadZeroExtend64(LoadSDNode *LD, unsigned Opcode,
98 SDNode *SelectIndexedLoadSignExtend64(LoadSDNode *LD, unsigned Opcode,
255 unsigned Opcode,
266 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::i32,
286 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32, MVT::Other,
308 unsigned Opcode,
320 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
343 SDNode *Result_1 = CurDAG->getMachineNode(Opcode, dl, MVT::i32,
376 unsigned Opcode = 0;
384 // Figure out the opcode
[all...] |
| /art/compiler/utils/arm/ |
| constants_arm.h | 133 enum Opcode {
154 std::ostream& operator<<(std::ostream& os, const Opcode& rhs);
284 Opcode OpcodeField() const {
285 return static_cast<Opcode>(Bits(kOpcodeShift, kOpcodeBits));
|
| /art/runtime/ |
| dex_instruction_visitor.h | 34 switch (inst->Opcode()) {
|
