/external/mesa3d/src/gallium/drivers/radeon/ |
R600InstrInfo.cpp | 301 // Note : we leave PRED* instructions there. 440 std::vector<MachineOperand> &Pred) const 456 const SmallVectorImpl<MachineOperand> &Pred) const 462 PMO.setReg(Pred[2].getReg());
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AMDGPUInstrInfo.cpp | 222 std::vector<MachineOperand> &Pred) const {
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AMDGPUInstrInfo.h | 120 std::vector<MachineOperand> &Pred) const;
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/external/llvm/include/llvm/IR/ |
BasicBlock.h | 266 /// \brief Notify the BasicBlock that the predecessor \p Pred is no longer 272 void removePredecessor(BasicBlock *Pred, bool DontDeleteUselessPHIs = false);
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/external/llvm/include/llvm/Transforms/Utils/ |
BasicBlockUtils.h | 240 BasicBlock *Pred);
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/external/llvm/lib/CodeGen/ |
Analysis.cpp | 163 ISD::CondCode llvm::getFCmpCondCode(FCmpInst::Predicate Pred) { 164 switch (Pred) { 200 ISD::CondCode llvm::getICmpCondCode(ICmpInst::Predicate Pred) { 201 switch (Pred) {
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LiveInterval.cpp | 801 for (const MachineBasicBlock *Pred : MBB->predecessors()) { 803 if (!Visited.insert(Pred).second) 806 VNI = searchForVNI(Indexes, LR, Pred, Visited); 830 for (const MachineBasicBlock *Pred : MBB->predecessors()) { 831 VNInfo *VNI = searchForVNI(Indexes, LI, Pred, Visited); [all...] |
/external/llvm/lib/CodeGen/SelectionDAG/ |
ResourcePriorityQueue.cpp | 219 SUnit &Pred = *I->getSUnit(); 220 if (!Pred.isScheduled) { 223 if (OnlyAvailablePred && OnlyAvailablePred != &Pred) 225 OnlyAvailablePred = &Pred;
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ScheduleDAGFast.cpp | 309 const SDep &Pred = LoadPreds[i]; 310 RemovePred(SU, Pred); 312 AddPred(LoadSU, Pred); 316 const SDep &Pred = NodePreds[i]; 317 RemovePred(SU, Pred); 318 AddPred(NewSU, Pred);
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/external/llvm/lib/Target/AMDGPU/ |
AMDGPUInstrInfo.h | 129 std::vector<MachineOperand> &Pred) const override;
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/external/llvm/lib/Target/ARM/ |
ARMBaseRegisterInfo.h | 163 int Val, ARMCC::CondCodes Pred = ARMCC::AL,
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Thumb2InstrInfo.cpp | 219 ARMCC::CondCodes Pred, unsigned PredReg, 224 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 241 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 248 .addImm((unsigned)Pred).addReg(PredReg).setMIFlags(MIFlags); 257 .addImm((unsigned)Pred).addReg(PredReg).addReg(0) 268 .addImm((unsigned)Pred).addReg(PredReg).addReg(0)
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ARMBaseRegisterInfo.cpp | 385 ARMCC::CondCodes Pred, 397 .addImm(0).addImm(Pred).addReg(PredReg) 734 ARMCC::CondCodes Pred = (PIdx == -1) 744 Offset, Pred, PredReg, TII); 748 Offset, Pred, PredReg, TII);
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/external/llvm/lib/Target/Hexagon/ |
HexagonMachineScheduler.cpp | 435 SUnit &Pred = *I->getSUnit(); 436 if (!Pred.isScheduled) { 439 if (OnlyAvailablePred && OnlyAvailablePred != &Pred) 441 OnlyAvailablePred = &Pred;
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/external/clang/lib/CodeGen/ |
CGCleanup.cpp | 465 llvm::BasicBlock *Pred = Entry->getSinglePredecessor(); 466 if (!Pred) return Entry; 468 llvm::BranchInst *Br = dyn_cast<llvm::BranchInst>(Pred->getTerminator()); 483 Entry->replaceAllUsesWith(Pred); 486 Pred->getInstList().splice(Pred->end(), Entry->getInstList()); 492 CGF.Builder.SetInsertPoint(Pred); 494 return Pred; [all...] |
/external/clang/lib/StaticAnalyzer/Checkers/ |
TestAfterDivZeroChecker.cpp | 74 const ExplodedNode *Pred, 98 const ExplodedNode *Pred,
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.11-4.8/x86_64-linux/include/c++/4.8/ext/pb_ds/detail/list_update_map_/ |
lu_map_.hpp | 238 template<typename Pred> 240 erase_if(Pred);
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/prebuilts/gcc/linux-x86/host/x86_64-linux-glibc2.15-4.8/x86_64-linux/include/c++/4.8/ext/pb_ds/detail/list_update_map_/ |
lu_map_.hpp | 238 template<typename Pred> 240 erase_if(Pred);
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/prebuilts/gcc/linux-x86/host/x86_64-w64-mingw32-4.8/x86_64-w64-mingw32/include/c++/4.8.3/ext/pb_ds/detail/list_update_map_/ |
lu_map_.hpp | 238 template<typename Pred> 240 erase_if(Pred);
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/prebuilts/ndk/current/sources/cxx-stl/gnu-libstdc++/4.9/include/ext/pb_ds/detail/list_update_map_/ |
lu_map_.hpp | 238 template<typename Pred> 240 erase_if(Pred);
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/external/llvm/lib/Target/Mips/ |
MipsAsmPrinter.cpp | 398 const MachineBasicBlock *Pred = *MBB->pred_begin(); 402 if (const BasicBlock *bb = Pred->getBasicBlock()) 419 if (!Pred->isLayoutSuccessor(MBB)) 423 if (Pred->empty()) 428 MachineBasicBlock::const_iterator I = Pred->end(); 429 while (I != Pred->begin() && !(--I)->isTerminator()) ; [all...] |
MipsDelaySlotFiller.cpp | 241 /// Examine Pred and see if it is possible to insert an instruction into 243 bool examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 849 bool Filler::examinePred(MachineBasicBlock &Pred, const MachineBasicBlock &Succ, 853 getBranch(Pred, Succ); 863 RegDU.addLiveOut(Pred, Succ); 866 BrMap[&Pred] = P.second;
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/external/llvm/lib/Transforms/Scalar/ |
EarlyCSE.cpp | 115 CmpInst::Predicate Pred = CI->getPredicate(); 118 Pred = CI->getSwappedPredicate(); 120 return hash_combine(Inst->getOpcode(), Pred, LHS, RHS); 520 if (BasicBlock *Pred = BB->getSinglePredecessor()) 521 if (auto *BI = dyn_cast<BranchInst>(Pred->getTerminator())) 535 BasicBlockEdge(Pred, BB)); [all...] |
DeadStoreElimination.cpp | 724 BasicBlock *Pred = *I; 725 if (Pred == BB) continue; 726 TerminatorInst *PredTI = Pred->getTerminator(); 730 if (DT->isReachableFromEntry(Pred)) 731 Blocks.push_back(Pred); [all...] |
/external/llvm/lib/Transforms/Utils/ |
SimplifyCFG.cpp | 136 BasicBlock *Pred, 647 BasicBlock *Pred, 649 Value *PredVal = isValueEqualityComparison(Pred->getTerminator()); 659 // Find out information about when control will move from Pred to TI's block. 661 BasicBlock *PredDef = GetValueEqualityComparisonCases(Pred->getTerminator(), 670 // If TI's block is the default block from Pred's comparison, potentially 690 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator() 703 DEBUG(dbgs() << "Threading pred instr: " << *Pred->getTerminator( [all...] |