| /external/clang/test/OpenMP/ |
| taskloop_simd_linear_messages.cpp | 91 class S5 {
93 S5():a(0) {}
95 S5(int v):a(v) { }
194 S5 g(5); // expected-note {{'g' defined here}}
228 // expected-error@+1 {{argument of a linear clause should be of integral or pointer type, not 'S5'}}
|
| /external/clang/test/Parser/ |
| MicrosoftExtensions.c | 78 struct __declspec(deprecated frobble "testing") S5 {}; /* expected-warning {{__declspec attribute 'frobble' is not supported}} expected-warning {{__declspec attribute '"testing"' is not supported}} */
|
| cxx0x-ambig.cpp | 62 struct S5 {
|
| /libcore/ojluni/src/main/java/sun/misc/ |
| FormattedFloatingDecimal.java | 700 int S2, S5; // powers of 2 and powers of 5, respectively, in S
709 S5 = Math.max( 0, decExp );
710 S2 = S5 + nTinyBits;
777 tenSbits = S2+1 + (( (S5+1) < n5bits.length )? n5bits[(S5+1)] : ( (S5+1)*3 ));
782 int s = small5pow[S5] << S2;
835 long s = long5pow[S5] << S2;
[all...] |
| /art/compiler/jni/quick/mips/ |
| calling_convention_mips.cc | 168 callee_save_regs_.push_back(MipsManagedRegister::FromCoreRegister(S5));
177 result = 1 << S2 | 1 << S3 | 1 << S4 | 1 << S5 | 1 << S6 | 1 << S7 | 1 << FP | 1 << RA;
|
| /libcore/ojluni/src/main/java/java/lang/ |
| FloatingDecimal.java | 633 int S2, S5; // powers of 2 and powers of 5, respectively, in S
642 S5 = Math.max( 0, decExp );
643 S2 = S5 + nTinyBits;
710 tenSbits = S2+1 + (( (S5+1) < n5bits.length )? n5bits[(S5+1)] : ( (S5+1)*3 ));
715 int s = small5pow[S5] << S2;
768 long s = long5pow[S5] << S2;
828 Sval = constructPow52( S5, S2 );
[all...] |
| /art/runtime/arch/arm/ |
| context_arm.cc | 86 fprs_[S5] = nullptr;
|
| quick_method_frame_info_arm.h | 42 (1 << art::arm::S4) | (1 << art::arm::S5) | (1 << art::arm::S6) | (1 << art::arm::S7) |
|
| /external/clang/test/CodeGenCXX/ |
| mangle.cpp | 116 template<int I> struct S5 { };
118 template<int I> void ft4(S5<I>) { }
121 ft4(S5<10>());
124 ft4(S5<20>());
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64CallingConvention.h | 35 AArch64::S3, AArch64::S4, AArch64::S5,
|
| AArch64PBQPRegAlloc.cpp | 50 case AArch64::S5:
|
| /external/clang/test/SemaTemplate/ |
| instantiate-local-class.cpp | 297 template <class T> struct S5 {
303 template struct S5<int>;
|
| /external/clang/test/CXX/drs/ |
| dr0xx.cpp | 95 struct S5 : S3, S4 {
96 S5();
97 ~S5();
99 S5::S5() {}
|
| /art/compiler/jni/quick/arm/ |
| calling_convention_arm.cc | 31 S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15
|
| /art/compiler/jni/quick/arm64/ |
| calling_convention_arm64.cc | 38 S0, S1, S2, S3, S4, S5, S6, S7
|
| /external/clang/test/SemaCXX/ |
| destructor.cpp | 160 struct S5 : public B {
|
| /external/llvm/lib/Target/ARM/ |
| ARMCallingConv.h | 166 ARM::S4, ARM::S5, ARM::S6, ARM::S7,
|
| /art/compiler/optimizing/ |
| code_generator_mips.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, FP, RA };
|
| code_generator_mips64.h | 55 { S0, S1, S2, S3, S4, S5, S6, S7, GP, S8, RA }; // TODO: review
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| code_generator_arm.h | 40 { S0, S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12, S13, S14, S15 };
|
| /art/compiler/utils/arm64/ |
| managed_register_arm64_test.cc | 231 reg = Arm64ManagedRegister::FromSRegister(S5);
239 EXPECT_EQ(S5, reg.AsSRegister());
241 EXPECT_TRUE(reg.Equals(Arm64ManagedRegister::FromSRegister(S5)));
[all...] |
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 1021 @S5 S6 S7 S8 A5 A6 A7 A8
1082 @Q10 S8 S5 A8 A5 S7 S4 A7 A4
1091 @Q10 S8 S5 A8 A5 S7 S4 A7 A
[all...] |
| /external/opencv3/modules/imgproc/src/ |
| imgwarp.cpp | [all...] |
| /external/valgrind/none/tests/arm/ |
| vfp.c | 623 #define TESTINSN_vpush_vpop_f32(S1, Sval1, S2, Sval2, S3, Sval3, S4, S5, S6) \
629 "vmov "#S5", %4\n\t" \
637 "vpop {"#S5", "#S6"}\n\t" \
643 "vstmia %0!, {"#S5"}\n\t" \
648 : #S1, #S2, #S3, #S4, #S5, #S6, "r4", "memory" \
651 #S5" 0x%08x "#S6" 0x%08x\n", out[0], out[1],\
870 "vldmdb r1!, {s5, s6}\n\t"
876 "vmov r1, s5\n\t"
1047 "s0", "s1", "s2", "s3", "s5", "s6", "s16", "s17",
[all...] |
| /art/compiler/utils/mips/ |
| assembler_mips_test.cc | 78 registers_.push_back(new mips::Register(mips::S5));
111 secondary_register_names_.emplace(mips::Register(mips::S5), "s5");
[all...] |
