| /external/mesa3d/src/gallium/auxiliary/gallivm/ |
| lp_bld_debug.cpp | 217 const MCSubtargetInfo *STI = T->createMCSubtargetInfo(Triple, sys::getHostCPUName(), "");
218 OwningPtr<const MCDisassembler> DisAsm(T->createMCDisassembler(*STI));
251 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *MII, *MRI, *STI));
254 T->createMCInstPrinter(AsmPrinterVariant, *AsmInfo, *STI));
|
| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 63 const MCSubtargetInfo &STI;
67 SIMCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
69 : MCII(mcii), STI(sti), Ctx(ctx) { }
126 const MCSubtargetInfo &STI,
128 return new SIMCCodeEmitter(MCII, STI, Ctx);
|
| /external/llvm/lib/Target/X86/AsmParser/ |
| X86AsmInstrumentation.cpp | 180 X86AddressSanitizer(const MCSubtargetInfo *&STI)
181 : X86AsmInstrumentation(STI), RepPrefix(false), OrigSPOffset(0) {}
259 return STI->getFeatureBits()[X86::Mode64Bit];
262 return STI->getFeatureBits()[X86::Mode32Bit];
265 return STI->getFeatureBits()[X86::Mode16Bit];
501 X86AddressSanitizer32(const MCSubtargetInfo *&STI)
502 : X86AddressSanitizer(STI) {}
759 X86AddressSanitizer64(const MCSubtargetInfo *&STI)
760 : X86AddressSanitizer(STI) {}
[all...] |
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsTargetStreamer.cpp | 437 const MCSubtargetInfo &STI)
438 : MipsTargetStreamer(S), MicroMipsEnabled(false), STI(STI) {
442 const FeatureBitset &Features = STI.getFeatureBits();
524 const FeatureBitset &Features = STI.getFeatureBits();
766 getStreamer().EmitInstruction(TmpInst, STI);
776 getStreamer().EmitInstruction(TmpInst, STI);
784 getStreamer().EmitInstruction(TmpInst, STI);
804 getStreamer().EmitInstruction(Inst, STI);
832 getStreamer().EmitInstruction(Inst, STI);
[all...] |
| MipsMCTargetDesc.cpp | 128 createMipsObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
129 return new MipsTargetELFStreamer(S, STI);
|
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.cpp | 40 static unsigned computeReturnSaveOffset(const PPCSubtarget &STI) {
41 if (STI.isDarwinABI())
42 return STI.isPPC64() ? 16 : 8;
44 return STI.isPPC64() ? 16 : 4;
47 static unsigned computeTOCSaveOffset(const PPCSubtarget &STI) {
48 return STI.isELFv2ABI() ? 24 : 40;
51 static unsigned computeFramePointerSaveOffset(const PPCSubtarget &STI) {
57 if (STI.isDarwinABI())
58 return STI.isPPC64() ? -8U : -4U;
61 return STI.isPPC64() ? -8U : -4U
[all...] |
| PPCFrameLowering.h | 57 PPCFrameLowering(const PPCSubtarget &STI);
|
| PPCVSXFMAMutate.cpp | 328 const PPCSubtarget &STI = MF.getSubtarget<PPCSubtarget>();
329 if (!STI.hasVSX())
334 TII = STI.getInstrInfo();
|
| /external/llvm/include/llvm/Target/ |
| TargetMachine.h | 102 const MCSubtargetInfo *STI;
166 const MCSubtargetInfo *getMCSubtargetInfo() const { return STI; }
|
| /external/llvm/lib/Target/ARM/ |
| ARMInstrInfo.cpp | 32 ARMInstrInfo::ARMInstrInfo(const ARMSubtarget &STI)
33 : ARMBaseInstrInfo(STI), RI() {}
|
| Thumb1InstrInfo.cpp | 24 Thumb1InstrInfo::Thumb1InstrInfo(const ARMSubtarget &STI)
25 : ARMBaseInstrInfo(STI), RI() {}
|
| ARMFrameLowering.h | 24 const ARMSubtarget &STI;
27 explicit ARMFrameLowering(const ARMSubtarget &sti);
|
| MLxExpansionPass.cpp | 384 const ARMSubtarget *STI = &Fn.getSubtarget<ARMSubtarget>();
386 if (!STI->isCortexA9())
388 isLikeA9 = STI->isLikeA9() || STI->isSwift();
389 isSwift = STI->isSwift();
|
| /external/llvm/lib/Target/ |
| TargetMachine.cpp | 45 MII(nullptr), STI(nullptr), RequireStructuredCFG(false),
53 delete STI;
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.cpp | 30 WebAssemblyInstrInfo::WebAssemblyInstrInfo(const WebAssemblySubtarget &STI)
33 RI(STI.getTargetTriple()) {}
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 28 X86FrameLowering(const X86Subtarget &STI, unsigned StackAlignOverride);
32 const X86Subtarget &STI;
|
| /external/llvm/include/llvm/MC/ |
| MCInstPrinter.h | 73 const MCSubtargetInfo &STI) = 0;
|
| MCWinCOFFStreamer.h | 73 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
|
| /external/llvm/lib/Target/BPF/ |
| BPFISelLowering.h | 37 explicit BPFTargetLowering(const TargetMachine &TM, const BPFSubtarget &STI);
|
| /external/llvm/lib/Target/BPF/InstPrinter/ |
| BPFInstPrinter.cpp | 30 StringRef Annot, const MCSubtargetInfo &STI) {
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.cpp | 30 StringRef Annot, const MCSubtargetInfo &STI) {
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.h | 26 explicit MipsSEInstrInfo(const MipsSubtarget &STI);
|
| /external/llvm/lib/Target/NVPTX/ |
| NVPTXPrologEpilogPass.cpp | 51 const TargetSubtargetInfo &STI = MF.getSubtarget();
52 const TargetFrameLowering &TFI = *STI.getFrameLowering();
53 const TargetRegisterInfo &TRI = *STI.getRegisterInfo();
|
| /external/llvm/lib/CodeGen/ |
| MachineCombiner.cpp | 445 const TargetSubtargetInfo &STI = MF.getSubtarget();
446 TII = STI.getInstrInfo();
447 TRI = STI.getRegisterInfo();
448 SchedModel = STI.getSchedModel();
449 TSchedModel.init(SchedModel, &STI, TII);
|
| /external/llvm/lib/Target/SystemZ/Disassembler/ |
| SystemZDisassembler.cpp | 26 SystemZDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx)
27 : MCDisassembler(STI, Ctx) {}
38 const MCSubtargetInfo &STI,
40 return new SystemZDisassembler(STI, Ctx);
378 return decodeInstruction(Table, MI, Inst, Address, this, STI);
|
