| /external/llvm/lib/Target/Mips/ |
| MipsTargetStreamer.h | 216 const MCSubtargetInfo &STI;
222 MipsTargetELFStreamer(MCStreamer &S, const MCSubtargetInfo &STI);
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| Mips16InstrInfo.cpp | 34 Mips16InstrInfo::Mips16InstrInfo(const MipsSubtarget &STI)
35 : MipsInstrInfo(STI, Mips::Bimm16), RI() {}
453 const MipsInstrInfo *llvm::createMips16InstrInfo(const MipsSubtarget &STI) {
454 return new Mips16InstrInfo(STI);
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| MipsISelLowering.h | 224 const MipsSubtarget &STI);
227 const MipsSubtarget &STI);
589 const MipsSubtarget &STI);
592 const MipsSubtarget &STI);
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| /external/llvm/lib/Target/PowerPC/MCTargetDesc/ |
| PPCMCTargetDesc.cpp | 227 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
228 const Triple &TT = STI.getTargetTriple();
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.h | 100 explicit PPCInstrInfo(PPCSubtarget &STI);
109 CreateTargetHazardRecognizer(const TargetSubtargetInfo *STI,
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| /external/llvm/lib/Target/SystemZ/ |
| SystemZInstrInfo.h | 119 SystemZSubtarget &STI;
137 explicit SystemZInstrInfo(SystemZSubtarget &STI);
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| /external/llvm/lib/Target/X86/InstPrinter/ |
| X86ATTInstPrinter.cpp | 41 StringRef Annot, const MCSubtargetInfo &STI) {
60 (STI.getFeatureBits()[X86::Mode64Bit])) {
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| /external/llvm/include/llvm/MC/ |
| MCAssembler.h | 268 /// STI - The MCSubtargetInfo in effect when the instruction was encoded.
269 const MCSubtargetInfo &STI;
272 MCRelaxableFragment(const MCInst &Inst, const MCSubtargetInfo &STI,
275 Inst(Inst), STI(STI) {}
280 const MCSubtargetInfo &getSubtargetInfo() { return STI; }
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| MCObjectStreamer.h | 100 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo& STI) override;
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| /external/llvm/lib/CodeGen/ |
| EarlyIfConversion.cpp | 789 const TargetSubtargetInfo &STI = MF.getSubtarget();
790 if (!STI.enableEarlyIfConversion())
793 TII = STI.getInstrInfo();
794 TRI = STI.getRegisterInfo();
795 SchedModel = STI.getSchedModel();
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| MachineFunction.cpp | 65 : Fn(F), Target(TM), STI(TM.getSubtargetImpl(*F)), Ctx(mmi.getContext()),
67 if (STI->getRegisterInfo())
74 MachineFrameInfo(STI->getFrameLowering()->getStackAlignment(),
75 STI->getFrameLowering()->isStackRealignable(),
82 Alignment = STI->getTargetLowering()->getMinFunctionAlignment();
88 STI->getTargetLowering()->getPrefFunctionAlignment());
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 684 const ARMSubtarget &STI = Fn.getSubtarget<ARMSubtarget>();
687 if (!(STI.isCortexA15() && STI.hasNEON()))
689 TII = STI.getInstrInfo();
690 TRI = STI.getRegisterInfo();
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| ARMLoadStoreOptimizer.cpp | 81 const ARMSubtarget *STI;
685 !STI->hasV6Ops()) {
[all...] |
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCChecker.cpp | 222 HexagonMCChecker::HexagonMCChecker(MCInstrInfo const &MCII, MCSubtargetInfo const &STI, MCInst &mcb, MCInst &mcbdx,
224 : MCB(mcb), MCBDX(mcbdx), RI(ri), MCII(MCII), STI(STI),
503 HexagonMCShuffler MCS(MCII, STI, MCB);
512 HexagonMCShuffler MCSDX(MCII, STI, MCBDX);
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| HexagonShuffler.cpp | 153 MCSubtargetInfo const &STI)
154 : MCII(MCII), STI(STI) {
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| HexagonMCInstrInfo.cpp | 59 MCSubtargetInfo const &STI,
70 HexagonMCShuffle(MCII, STI, MCB);
77 HexagonMCShuffle(MCII, STI, Context, MCB, possibleDuplexes);
86 HexagonMCShuffle(MCII, STI, MCB);
320 MCSubtargetInfo const &STI,
323 const InstrItinerary *II = STI.getSchedModel().InstrItineraries;
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| /external/llvm/lib/MC/ |
| MCMachOStreamer.cpp | 50 void EmitInstToData(const MCInst &Inst, const MCSubtargetInfo &STI) override;
434 const MCSubtargetInfo &STI) {
440 getAssembler().getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI);
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| MCELFStreamer.cpp | 464 const MCSubtargetInfo &STI) {
465 this->MCObjectStreamer::EmitInstToFragment(Inst, STI);
473 const MCSubtargetInfo &STI) {
478 Assembler.getEmitter().encodeInstruction(Inst, VecOS, Fixups, STI);
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| ResourcePriorityQueue.cpp | 46 const TargetSubtargetInfo &STI = IS->MF->getSubtarget();
47 TRI = STI.getRegisterInfo();
49 TII = STI.getInstrInfo();
50 ResourcesModel.reset(TII->CreateTargetScheduleState(STI));
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| /external/llvm/lib/Target/AMDGPU/InstPrinter/ |
| AMDGPUInstPrinter.h | 33 const MCSubtargetInfo &STI) override;
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| /external/llvm/lib/Target/AMDGPU/ |
| SIRegisterInfo.cpp | 127 const AMDGPUSubtarget &STI = MF.getSubtarget<AMDGPUSubtarget>();
129 unsigned SGPRLimit = getNumSGPRsAllowed(STI.getGeneration(),
130 STI.getMaxWavesPerCU());
131 unsigned VGPRLimit = getNumVGPRsAllowed(STI.getMaxWavesPerCU());
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| /external/llvm/lib/Target/Hexagon/ |
| HexagonMachineScheduler.cpp | 212 const TargetSubtargetInfo &STI = DAG->MF.getSubtarget();
213 const TargetInstrInfo *TII = STI.getInstrInfo();
221 Top.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
222 Bot.ResourceModel = new VLIWResourceModel(STI, DAG->getSchedModel());
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| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.h | 73 const MSP430Subtarget &STI);
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| /external/llvm/lib/Target/Sparc/MCTargetDesc/ |
| SparcMCTargetDesc.cpp | 125 createObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
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| /external/mesa3d/src/gallium/drivers/radeon/MCTargetDesc/ |
| R600MCCodeEmitter.cpp | 43 const MCSubtargetInfo &STI;
48 R600MCCodeEmitter(const MCInstrInfo &mcii, const MCSubtargetInfo &sti,
50 : MCII(mcii), STI(sti), Ctx(ctx) { }
145 const MCSubtargetInfo &STI,
147 return new R600MCCodeEmitter(MCII, STI, Ctx);
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