| /external/llvm/lib/Target/X86/Disassembler/ |
| X86Disassembler.h | 96 X86GenericDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
|
| /external/llvm/lib/Target/X86/ |
| X86ExpandPseudo.cpp | 44 const X86Subtarget *STI;
94 bool IsWin64 = STI->isTargetWin64();
137 STI->isTarget64BitLP64() || STI->isTargetNaCl64();
151 TII->get(STI->is64Bit() ? X86::IRET64 : X86::IRET32));
184 STI = &static_cast<const X86Subtarget &>(MF.getSubtarget());
185 TII = STI->getInstrInfo();
186 TRI = STI->getRegisterInfo();
187 X86FL = STI->getFrameLowering();
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| X86FrameLowering.cpp | 38 X86FrameLowering::X86FrameLowering(const X86Subtarget &STI,
41 STI.is64Bit() ? -8 : -4),
42 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
45 Is64Bit = STI.is64Bit();
46 IsLP64 = STI.isTarget64BitLP64();
48 Uses64BitFramePtr = STI.isTarget64BitLP64() || STI.isTargetNaCl64()
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.cpp | 373 MipsSEFrameLowering::MipsSEFrameLowering(const MipsSubtarget &STI)
374 : MipsFrameLowering(STI, STI.stackAlignment()) {}
383 *static_cast<const MipsSEInstrInfo *>(STI.getInstrInfo());
385 *static_cast<const MipsRegisterInfo *>(STI.getRegisterInfo());
389 MipsABIInfo ABI = STI.getABI();
445 if (!STI.isLittle())
461 if (!STI.isLittle())
528 unsigned BP = STI.isABI_N64() ? Mips::S7_64 : Mips::S7;
549 if (!STI.hasMips32r2()
[all...] |
| Mips16FrameLowering.h | 22 explicit Mips16FrameLowering(const MipsSubtarget &STI);
|
| MipsSEFrameLowering.h | 23 explicit MipsSEFrameLowering(const MipsSubtarget &STI);
|
| /external/llvm/lib/CodeGen/ |
| TargetSchedule.cpp | 54 const TargetSubtargetInfo *sti,
57 STI = sti;
59 STI->initInstrItins(InstrItins);
116 SchedClass = STI->resolveSchedClass(SchedClass, MI, this);
192 STI->getWriteLatencyEntry(SCDesc, DefIdx);
203 int Advance = STI->getReadAdvanceCycles(UseDesc, UseIdx, WriteID);
232 STI->getWriteLatencyEntry(&SCDesc, DefIdx);
293 for (const MCWriteProcResEntry *PRI = STI->getWriteProcResBegin(SCDesc),
294 *PRE = STI->getWriteProcResEnd(SCDesc); PRI != PRE; ++PRI)
[all...] |
| /external/llvm/lib/Target/AMDGPU/MCTargetDesc/ |
| SIMCCodeEmitter.cpp | 56 const MCSubtargetInfo &STI) const override;
61 const MCSubtargetInfo &STI) const override;
67 const MCSubtargetInfo &STI) const override;
183 const MCSubtargetInfo &STI) const {
185 uint64_t Encoding = getBinaryCodeForInstr(MI, Fixups, STI);
230 const MCSubtargetInfo &STI) const {
240 return getMachineOpValue(MI, MO, Fixups, STI);
246 const MCSubtargetInfo &STI) const {
|
| /external/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsELFStreamer.cpp | 19 const MCSubtargetInfo &STI) {
20 MCELFStreamer::EmitInstruction(Inst, STI);
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| MipsELFStreamer.h | 49 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
|
| /external/llvm/tools/llvm-mc/ |
| Disassembler.cpp | 38 const MCSubtargetInfo &STI) {
72 Streamer.EmitInstruction(Inst, STI);
135 MCSubtargetInfo &STI,
157 T.createMCDisassembler(STI, Ctx));
202 InAtomicBlock, STI);
|
| /external/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 437 static bool isThumb(const MCSubtargetInfo& STI) {
438 return STI.getFeatureBits()[ARM::ModeThumb];
610 const ARMSubtarget STI(TT, CPU, ArchFS, ATM, ATM.isLittleEndian());
612 std::string CPUString = STI.getCPUString();
616 if (STI.isKrait()) {
620 if (STI.hasDivide() || STI.hasDivideInARMMode())
626 ATS.emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(CPUString, &STI));
630 if (STI.hasV7Ops()) {
631 if (STI.isAClass())
[all...] |
| Thumb1InstrInfo.h | 26 explicit Thumb1InstrInfo(const ARMSubtarget &STI);
|
| /external/llvm/lib/MC/MCDisassembler/ |
| Disassembler.cpp | 59 const MCSubtargetInfo *STI =
61 if (!STI)
70 MCDisassembler *DisAsm = TheTarget->createMCDisassembler(*STI, *Ctx);
92 TheTarget, MAI, MRI, STI, MII, Ctx, DisAsm, IP);
163 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
164 InstrItineraryData IID = STI->getInstrItineraryForCPU(DC->getCPU());
182 const MCSubtargetInfo *STI = DC->getSubtargetInfo();
183 const MCSchedModel SCModel = STI->getSchedModel();
206 const MCWriteLatencyEntry *WLEntry = STI->getWriteLatencyEntry(SCDesc,
|
| /external/llvm/lib/Object/ |
| RecordStreamer.h | 32 void EmitInstruction(const MCInst &Inst, const MCSubtargetInfo &STI) override;
|
| RecordStreamer.cpp | 71 const MCSubtargetInfo &STI) {
72 MCStreamer::EmitInstruction(Inst, STI);
|
| /external/llvm/lib/Target/AArch64/MCTargetDesc/ |
| AArch64ELFStreamer.cpp | 110 const MCSubtargetInfo &STI) override {
112 MCELFStreamer::EmitInstruction(Inst, STI);
199 createAArch64ObjectTargetStreamer(MCStreamer &S, const MCSubtargetInfo &STI) {
200 const Triple &TT = STI.getTargetTriple();
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUMCInstLower.cpp | 88 const AMDGPUSubtarget &STI = MF->getSubtarget<AMDGPUSubtarget>();
89 AMDGPUMCInstLower MCInstLowering(OutContext, STI);
93 if (!STI.getInstrInfo()->verifyInstruction(MI, Err)) {
110 if (STI.dumpCode()) {
|
| /external/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| HexagonMCELFStreamer.h | 31 const MCSubtargetInfo &STI) override;
|
| /external/llvm/lib/Target/MSP430/InstPrinter/ |
| MSP430InstPrinter.h | 29 const MCSubtargetInfo &STI) override;
|
| /external/llvm/lib/Target/WebAssembly/ |
| WebAssemblyInstrInfo.h | 33 explicit WebAssemblyInstrInfo(const WebAssemblySubtarget &STI);
|
| /external/llvm/lib/Target/XCore/InstPrinter/ |
| XCoreInstPrinter.h | 36 const MCSubtargetInfo &STI) override;
|
| /external/llvm/lib/Target/XCore/ |
| XCoreFrameLowering.h | 26 XCoreFrameLowering(const XCoreSubtarget &STI);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/bfin/ |
| event.s | 28 .global sti
29 sti: label
30 STI r1;
31 stI r2;
|
| /external/llvm/lib/Target/ARM/MCTargetDesc/ |
| ARMMCTargetDesc.cpp | 35 static bool getMCRDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
37 if (STI.getFeatureBits()[llvm::ARM::HasV7Ops] &&
67 static bool getITDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
69 if (STI.getFeatureBits()[llvm::ARM::HasV8Ops] && MI.getOperand(1).isImm() &&
79 static bool getARMStoreDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
81 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
96 static bool getARMLoadDeprecationInfo(MCInst &MI, const MCSubtargetInfo &STI,
98 assert(!STI.getFeatureBits()[llvm::ARM::ModeThumb] &&
|
