| /external/compiler-rt/lib/tsan/rtl/ |
| tsan_interface_atomic.cc | 282 // Strictly saying even relaxed store cuts off release sequence,
550 SCOPED_ATOMIC(Store, a, v, mo);
555 SCOPED_ATOMIC(Store, a, v, mo);
560 SCOPED_ATOMIC(Store, a, v, mo);
565 SCOPED_ATOMIC(Store, a, v, mo);
571 SCOPED_ATOMIC(Store, a, v, mo);
908 ATOMIC(Store, *(a32**)a, *(a32*)(a+8), mo_release);
913 ATOMIC(Store, *(a64**)a, *(a64*)(a+8), mo_release);
|
| /external/llvm/lib/Transforms/Scalar/ |
| RewriteStatepointsForGC.cpp | 513 // A CAS is effectively a atomic store and load combined under a
[all...] |
| /external/valgrind/VEX/priv/ |
| host_tilegx_defs.c | 169 "Store ",
350 UChar sz = instr->GXin.Store.sz;
353 ppTILEGXAMode(instr->GXin.Store.dst);
355 ppHRegTILEGX(instr->GXin.Store.src);
439 load and store since TileGx has no pre-displacement
897 i->GXin.Store.sz = sz;
898 i->GXin.Store.src = src;
899 i->GXin.Store.dst = dst;
1056 addHRegUse(u, HRmRead, i->GXin.Store.src);
1057 addRegUsage_TILEGXAMode(u, i->GXin.Store.dst)
[all...] |
| host_amd64_defs.c | 773 i->Ain.Store.sz = sz;
774 i->Ain.Store.src = src;
775 i->Ain.Store.dst = dst;
[all...] |
| host_x86_defs.c | 704 i->Xin.Store.sz = sz;
705 i->Xin.Store.src = src;
706 i->Xin.Store.dst = dst;
[all...] |
| /external/v8/test/cctest/compiler/ |
| codegen-tester.cc | 635 m.Store(MachineTypeForC<int64_t>().representation(),
645 m.Store(MachineTypeForC<double>().representation(),
657 m.Store(MachineTypeForC<int64_t>().representation(),
675 m.Store(
698 m.Store(MachineTypeForC<int64_t>().representation(),
|
| /art/compiler/jni/quick/ |
| jni_compiler.cc | 292 __ Store(saved_cookie_offset, main_jni_conv->IntReturnRegister(), 4);
393 __ Store(return_save_location, main_jni_conv->ReturnRegister(), main_jni_conv->SizeOfReturnValue());
581 // regular non-straddling store
582 __ Store(out_off, in_reg, param_size);
584 // store where input straddles registers and stack
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64TargetTransformInfo.cpp | 83 case Instruction::Store:
415 if (Opcode == Instruction::Store && Src->isVectorTy() && Alignment != 16 &&
468 Cost += getMemoryOpCost(Instruction::Store, I, 128, 0) +
|
| /packages/apps/Email/provider_src/com/android/email/mail/store/ |
| ImapStore.java | 17 package com.android.email.mail.store;
28 import com.android.email.mail.Store;
29 import com.android.email.mail.store.imap.ImapConstants;
30 import com.android.email.mail.store.imap.ImapResponse;
31 import com.android.email.mail.store.imap.ImapString;
82 public class ImapStore extends Store {
99 public static Store newInstance(Account account, Context context) throws MessagingException {
104 * Creates a new store for the given account. Always use
105 * {@link #newInstance(Account, Context)} to create an IMAP store.
214 // This section is per Store, and adds in a dynamic elements like UID's
[all...] |
| Pop3Store.java | 17 package com.android.email.mail.store;
23 import com.android.email.mail.Store;
52 public class Pop3Store extends Store {
67 public static Store newInstance(Account account, Context context) throws MessagingException {
72 * Creates a new store for the given account.
|
| /external/v8/src/compiler/ |
| code-assembler.cc | 266 Node* CodeAssembler::Store(MachineRepresentation rep, Node* base, Node* value) {
267 return raw_assembler_->Store(rep, base, value, kFullWriteBarrier);
270 Node* CodeAssembler::Store(MachineRepresentation rep, Node* base, Node* index,
272 return raw_assembler_->Store(rep, base, index, value, kFullWriteBarrier);
277 return raw_assembler_->Store(rep, base, value, kNoWriteBarrier);
282 return raw_assembler_->Store(rep, base, index, value, kNoWriteBarrier);
|
| /art/compiler/utils/ |
| assembler.h | 109 template<typename T> void Store(size_t position, T value) {
387 // Store routines
388 virtual void Store(FrameOffset offs, ManagedRegister src, size_t size) = 0;
|
| /external/libhevc/common/arm/ |
| ihevc_sao_band_offset_luma.s | 89 STRB r11,[r2],#1 @Store the value in pu1_src_left pointer
103 STRB r10,[r4] @store to pu1_src_top_left[0]
114 VST1.8 D0,[r3]! @Store to pu1_src_top[col]
|
| /external/llvm/lib/Target/AMDGPU/ |
| AMDGPUPromoteAlloca.cpp | 143 case Instruction::Store: {
218 case Instruction::Store: {
|
| /external/llvm/test/MC/AArch64/ |
| arm64-memory.s | 279 ; Load/Store pair (indexed, offset)
311 ; Load/Store pair (pre-indexed)
339 ; Load/Store pair (post-indexed)
367 ; Load/Store pair (no-allocate)
391 ; Load/Store register offset
453 ; Load/Store exclusive
483 ; Load-acquire/Store-release non-exclusive
507 ; Load-acquire/Store-release exclusive
|
| /external/v8/tools/turbolizer/ |
| node.js | 40 (this.opcode.startsWith('Store') && this.opcode.length > 5);
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| 24k-triple-stores-1.d | 3 #name: 24K: Triple Store (Opcode Check)
|
| micromips@24k-triple-stores-1.d | 3 #name: 24K: Triple Store (Opcode Check)
|
| micromips@24k-triple-stores-3.d | 3 #name: 24K: Triple Store (Double-word Check)
|
| micromips@24k-triple-stores-7.d | 3 #name: 24K: Triple Store (Extended Range Check)
|
| /external/clang/include/clang/Analysis/Analyses/ |
| ThreadSafetyTraverse.h | 135 // Container is a minimal interface used to store results when traversing
213 R_SExpr reduceStore(Store &Orig, R_SExpr E0, R_SExpr E1) { return E0 && E1; }
214 R_SExpr reduceArrayIndex(Store &Orig, R_SExpr E0, R_SExpr E1) {
217 R_SExpr reduceArrayAdd(Store &Orig, R_SExpr E0, R_SExpr E1) {
739 void printStore(const Store *E, StreamType &SS) {
|
| /external/google-breakpad/src/processor/ |
| static_address_map_unittest.cc | 79 addr_map[testcase].Store(testdata[testcase][data_item], sstream.str());
|
| /external/llvm/include/llvm/CodeGen/ |
| BasicTTIImpl.h | 492 // itself. Unless the corresponding extending load or truncating store is
496 if (Opcode == Instruction::Store)
502 // This is a vector load/store for some illegal type that is scalarized.
504 Cost += getScalarizationOverhead(Src, Opcode != Instruction::Store,
505 Opcode == Instruction::Store);
526 // Firstly, the cost of load/store operation.
563 // E.g. An interleaved store of factor 2:
565 // store <8 x i32> %interleaved.vec, <8 x i32>* %ptr
686 ->getMaskedMemoryOpCost(Instruction::Store, Tys[0], 0, 0);
|
| /external/llvm/lib/Analysis/ |
| CaptureTracking.cpp | 164 // to determine whether this store is not actually an escape point.
267 case Instruction::Store:
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZTargetTransformInfo.cpp | 89 case Instruction::Store:
91 // Any 8-bit immediate store can by implemented via mvi.
|
