| /external/valgrind/VEX/priv/ |
| host_mips_defs.h | 299 Min_Store, /* store a 8|16|32 bit value to mem */
302 Min_StoreC, /* mips Store Conditional Word - SC */
309 Min_FpLdSt, /* FP load/store */
489 } Store;
|
| /external/valgrind/VEX/pub/ |
| libvex_ir.h | 253 /* IREndness is used in load IRExprs and store IRStmts. */
[all...] |
| /hardware/intel/common/omx-components/videocodec/libvpx_internal/libvpx/vp9/encoder/x86/ |
| vp9_subpel_variance.asm | 102 movd [r1], m7 ; store sse
104 movd rax, m6 ; store sum as return value
113 movd [r1], m7 ; store sse
116 movd rax, m6 ; store sum as return value
165 ;Store bilin_filter and pw_8 location in stack
182 ;Store bilin_filter and pw_8 location in stack
1041 ; have a 1-register shortage to be able to store the backup of the bilin
[all...] |
| /prebuilts/gdb/darwin-x86/include/python2.7/ |
| Python-ast.h | 11 typedef enum _expr_context { Load=1, Store=2, Del=3, AugLoad=4, AugStore=5,
|
| /prebuilts/gdb/linux-x86/include/python2.7/ |
| Python-ast.h | 11 typedef enum _expr_context { Load=1, Store=2, Del=3, AugLoad=4, AugStore=5,
|
| /prebuilts/python/darwin-x86/2.7.5/include/python2.7/ |
| Python-ast.h | 11 typedef enum _expr_context { Load=1, Store=2, Del=3, AugLoad=4, AugStore=5,
|
| /prebuilts/python/linux-x86/2.7.5/include/python2.7/ |
| Python-ast.h | 11 typedef enum _expr_context { Load=1, Store=2, Del=3, AugLoad=4, AugStore=5,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| SelectionDAG.cpp | 481 case ISD::STORE: {
[all...] |
| /external/llvm/lib/Target/Mips/ |
| MipsISelLowering.cpp | 245 // MIPS doesn't have extending float->double load/store. Set LoadExtAction
297 setOperationAction(ISD::STORE, MVT::i64, Custom);
[all...] |
| /external/v8/test/cctest/compiler/ |
| test-run-machops.cc | [all...] |
| /external/v8/src/x64/ |
| macro-assembler-x64.cc | 91 void MacroAssembler::Store(ExternalReference destination, Register source) {
217 // Load store buffer top.
221 // Store pointer to buffer.
767 // We don't allow a GC during a store buffer overflow so there is no need to
768 // store the registers in any particular way, but we do have to store and
1088 void MacroAssembler::Store(const Operand& dst, Register src, Representation r) {
[all...] |
| /art/runtime/arch/mips/ |
| quick_entrypoints_mips.S | 368 sw $zero, 0($sp) # Store null for ArtMethod* at bottom of frame
389 sw $v1, 4($a2) # store v0/v1 into result
391 SDu $f0, $f1, 0, $a2, $t0 # store f0/f1 into result
423 sw $ra, 0($t0) # Store RA per the compiler ABI
723 sw $zero, 0($sp) # store null for ArtMethod* at bottom of frame
742 sw $v0, 0($t0) # store the result
744 sw $v1, 4($t0) # store the other half of the result
746 SDu $f0, $f1, 0, $t0, $t1 # store floating point result
851 sw $zero, 0($sp) # store null for ArtMethod* at bottom of frame
[all...] |
| /art/runtime/arch/mips64/ |
| quick_entrypoints_mips64.S | 241 s.d $f12, 16($sp) # This isn't necessary to store.
409 sd $zero, 0($sp) # Store null for ArtMethod* at bottom of frame
430 sw $v0, 0($a3) # store low half of result
431 sw $v1, 4($a3) # store high half of result
465 sw $ra, 0($t0) # Store low half of RA per compiler ABI
467 sw $t1, 4($t0) # Store high half of RA per compiler ABI
805 sd $zero, 0($sp) # store null for ArtMethod* at bottom of frame
834 sw $v0, 0($a4) # store the result
837 sw $v1, 4($a4) # store the other half of the result
841 sw $v0, 0($a4) # store the resul
[all...] |
| /external/clang/lib/CodeGen/ |
| CGBuiltin.cpp | 242 // read as an i128. The "store" will put the higher-order double in the
[all...] |
| /external/libavc/encoder/arm/ |
| ime_distortion_metrics_a9q.s | 570 stmfd sp!, {r4-r11, lr} @store register values to stack
721 stmfd sp!, {r12, r14} @store register values to stack
[all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 425 // used. For each store instruction, calculate the set of used bits in
433 // Store byte
489 // Store low half
545 // Store high half
[all...] |
| /external/llvm/lib/Target/XCore/ |
| XCoreISelLowering.cpp | 139 setOperationAction(ISD::STORE, MVT::i32, Custom);
176 setTargetDAGCombine(ISD::STORE);
213 case ISD::STORE: return LowerSTORE(Op, DAG);
510 assert(!ST->isTruncatingStore() && "Unexpected store type");
511 assert(ST->getMemoryVT() == MVT::i32 && "Unexpected store EVT");
519 // Leave aligned store alone.
784 // Store the incremented VAList to the legalized pointer
[all...] |
| /external/skia/dm/ |
| Android.mk | 647 # Store skia's resources in the directory structure that the Android testing
|
| /external/v8/src/compiler/ |
| effect-control-linearizer.cc | 268 // Store the effect for later use.
[all...] |
| /external/valgrind/callgrind/ |
| main.c | 208 load-op-store instructions (x86, amd64), the insn is treated as if
1063 IRExpr* data = st->Ist.Store.data;
1064 IRExpr* aexpr = st->Ist.Store.addr;
[all...] |
| /external/valgrind/exp-sgcheck/ |
| sg_main.c | 446 /* no. clone it, store the clone and return the clone's
[all...] |
| /art/compiler/utils/arm/ |
| assembler_arm.cc | 281 // Encoding for vfp load/store addressing.
489 void ArmAssembler::Store(FrameOffset dest, ManagedRegister msrc, size_t size) {
[all...] |
| /art/compiler/utils/arm64/ |
| assembler_arm64.cc | 127 void Arm64Assembler::Store(FrameOffset offs, ManagedRegister m_src, size_t size) {
|
| /art/compiler/utils/mips/ |
| assembler_mips.h | 427 // Store routines.
428 void Store(FrameOffset offs, ManagedRegister msrc, size_t size) OVERRIDE;
[all...] |
| /art/compiler/utils/mips64/ |
| assembler_mips64.h | 379 // Store routines.
380 void Store(FrameOffset offs, ManagedRegister msrc, size_t size) OVERRIDE;
|
