| /external/llvm/lib/Target/Mips/ |
| MipsSEInstrInfo.cpp | 182 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
251 const TargetRegisterInfo *TRI, int64_t Offset) const {
632 const TargetRegisterInfo &TRI = getRegisterInfo();
657 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
678 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
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| MipsSEFrameLowering.cpp | 775 const TargetRegisterInfo *TRI) const {
814 const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
816 CSI[i].getFrameIdx(), RC, TRI);
837 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
838 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
[all...] |
| Mips16InstrInfo.cpp | 97 const TargetRegisterInfo *TRI,
115 const TargetRegisterInfo *TRI,
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| /external/llvm/include/llvm/CodeGen/ |
| MachineBasicBlock.h | 380 const uint32_t *getBeginClobberMask(const TargetRegisterInfo *TRI) const;
384 const uint32_t *getEndClobberMask(const TargetRegisterInfo *TRI) const;
725 LivenessQueryResult computeRegisterLiveness(const TargetRegisterInfo *TRI,
[all...] |
| MachineOperand.h | 221 void print(raw_ostream &os, const TargetRegisterInfo *TRI = nullptr) const;
223 const TargetRegisterInfo *TRI = nullptr) const;
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| LiveIntervalAnalysis.h | 56 const TargetRegisterInfo* TRI;
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| MachineScheduler.h | 46 // DAG->addMutation(new CustomDependencies(DAG->TII, DAG->TRI));
837 const TargetRegisterInfo *TRI;
842 Context(C), SchedModel(nullptr), TRI(nullptr) {}
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| CallingConvLower.h | 199 const TargetRegisterInfo &TRI;
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| /external/llvm/lib/CodeGen/ |
| ScheduleDAG.cpp | 40 TRI(mf.getSubtarget().getRegisterInfo()), MF(mf),
351 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
371 dbgs() << " Reg=" << PrintReg(I->getReg(), G->TRI);
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| MachineCombiner.cpp | 41 const TargetRegisterInfo *TRI;
447 TRI = STI.getRegisterInfo();
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| TargetLoweringBase.cpp | [all...] |
| MachineSink.cpp | 58 const TargetRegisterInfo *TRI;
265 TRI = MF.getSubtarget().getRegisterInfo();
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| /external/llvm/lib/CodeGen/SelectionDAG/ |
| FunctionLoweringInfo.cpp | 142 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
144 TLI->ParseConstraints(Fn->getParent()->getDataLayout(), TRI, CS);
151 TLI->getRegForInlineAsmConstraint(TRI, Op.ConstraintCode,
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| /external/llvm/lib/CodeGen/AsmPrinter/ |
| AsmPrinterInlineAsm.cpp | 143 const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
144 TAP->SetFrameRegister(TRI->getFrameRegister(*MF));
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| /external/llvm/lib/Target/AMDGPU/ |
| R600MachineScheduler.cpp | 31 TRI = static_cast<const R600RegisterInfo*>(DAG->TRI);
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| SIISelLowering.h | 123 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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| /external/llvm/lib/Target/Hexagon/ |
| BitTracker.h | 344 : TRI(T), MRI(M) {}
429 const TargetRegisterInfo &TRI;
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| HexagonVLIWPacketizer.cpp | 113 const MachineInstr *SecondI, const TargetRegisterInfo *TRI) {
118 if (SecondI->readsRegister(R, TRI))
314 const TargetRegisterInfo *TRI) {
316 for (auto *CSR = TRI->getCalleeSavedRegs(&MF); CSR && *CSR; ++CSR)
317 if (MI->modifiesRegister(*CSR, TRI))
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86SelectionDAGInfo.cpp | 29 // We cannot use TRI->hasBasePointer() until *after* we select all basic
38 const X86RegisterInfo *TRI = static_cast<const X86RegisterInfo *>(
40 unsigned BaseReg = TRI->getBaseRegister();
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| /external/llvm/lib/Target/XCore/ |
| XCoreInstrInfo.cpp | 364 const TargetRegisterInfo *TRI) const
386 const TargetRegisterInfo *TRI) const
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| XCoreISelLowering.h | 193 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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| /external/llvm/lib/Target/PowerPC/ |
| PPCInstrInfo.cpp | 820 const TargetRegisterInfo *TRI = &getRegisterInfo();
824 TRI->getMatchingSuperReg(DestReg, PPC::sub_64, &PPC::VSRCRegClass);
833 TRI->getMatchingSuperReg(DestReg, PPC::sub_128, &PPC::VSRCRegClass);
842 TRI->getMatchingSuperReg(SrcReg, PPC::sub_64, &PPC::VSRCRegClass);
851 TRI->getMatchingSuperReg(SrcReg, PPC::sub_128, &PPC::VSRCRegClass);
869 .addImm(TRI->getEncodingValue(CRReg) * 4 + (4 - getCRBitValue(SrcReg)))
[all...] |
| /external/llvm/lib/Target/Sparc/ |
| SparcISelLowering.h | 84 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
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| /external/llvm/lib/Target/ARM/ |
| ARMISelLowering.h | 335 getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
473 findRepresentativeClass(const TargetRegisterInfo *TRI,
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| /external/mesa3d/src/mesa/tnl_dd/ |
| t_dd_tritmp.h | 296 TRI( v[0], v[1], v[2] );
299 TRI( v[0], v[1], v[2] );
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