| /external/mesa3d/src/mesa/drivers/dri/i915/ |
| intel_tris.c | 554 #define TRI( a, b, c ) \
864 #define RENDER_TRI( v0, v1, v2 ) TRI( V(v0), V(v1), V(v2) )
[all...] |
| /external/cblas/testing/ |
| c_cblat2.f | [all...] |
| c_cblat3.f | [all...] |
| c_dblat2.f | [all...] |
| c_dblat3.f | [all...] |
| c_sblat2.f | [all...] |
| c_sblat3.f | [all...] |
| c_zblat2.f | [all...] |
| c_zblat3.f | [all...] |
| /external/eigen/blas/testing/ |
| cblat2.f | [all...] |
| dblat2.f | [all...] |
| dblat3.f | [all...] |
| sblat2.f | [all...] |
| sblat3.f | [all...] |
| zblat2.f | [all...] |
| cblat3.f | [all...] |
| zblat3.f | [all...] |
| /external/llvm/lib/Target/Hexagon/ |
| HexagonBitSimplify.cpp | 119 : RS(S), TRI(RI) {}
124 const TargetRegisterInfo *TRI;
132 OS << ' ' << PrintReg(R, P.TRI);
[all...] |
| HexagonHardwareLoops.cpp | 328 void print(raw_ostream &OS, const TargetRegisterInfo *TRI = nullptr) const {
329 if (isReg()) { OS << PrintReg(Contents.R.Reg, TRI, Contents.R.Sub); }
[all...] |
| HexagonISelLowering.cpp | [all...] |
| /external/llvm/lib/Target/MSP430/ |
| MSP430ISelLowering.cpp | 226 const TargetRegisterInfo *TRI, StringRef Constraint, MVT VT) const {
239 return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
[all...] |
| /external/llvm/lib/Target/X86/ |
| X86FloatingPoint.cpp | [all...] |
| /external/llvm/lib/Target/ARM/ |
| ARMFastISel.cpp | [all...] |
| /external/mesa3d/src/mesa/drivers/dri/r200/ |
| r200_swtcl.c | 388 #define TRI( a, b, c ) r200_triangle( rmesa, a, b, c )
|
| /external/mesa3d/src/mesa/drivers/dri/radeon/ |
| radeon_swtcl.c | 510 #define TRI( a, b, c ) radeon_triangle( rmesa, a, b, c )
|
