| /external/llvm/lib/CodeGen/ |
| InterferenceCache.h | 25 const TargetRegisterInfo *TRI;
113 void revalidate(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
116 bool valid(LiveIntervalUnion *LIUArray, const TargetRegisterInfo *TRI);
121 const TargetRegisterInfo *TRI,
153 : TRI(nullptr), LIUArray(nullptr), MF(nullptr), PhysRegEntries(nullptr),
|
| LiveVariables.cpp | 197 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
219 if (TRI->isSubRegister(Reg, DefReg)) {
220 for (MCSubRegIterator SubRegs(DefReg, TRI, /*IncludeSelf=*/true);
251 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
263 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
274 for (MCSubRegIterator SubRegs(Reg, TRI, /*IncludeSelf=*/true);
290 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
339 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
353 for (MCSubRegIterator SS(SubReg, TRI, /*IncludeSelf=*/true); SS.isValid();
369 PhysRegDef[Reg]->addRegisterDead(Reg, TRI, true)
[all...] |
| VirtRegMap.cpp | 59 TRI = mf.getSubtarget().getRegisterInfo();
125 OS << '[' << PrintReg(Reg, TRI) << " -> "
126 << PrintReg(Virt2PhysMap[Reg], TRI) << "] "
127 << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
134 OS << '[' << PrintReg(Reg, TRI) << " -> fi#" << Virt2StackSlotMap[Reg]
135 << "] " << TRI->getRegClassName(MRI->getRegClass(Reg)) << "\n";
160 const TargetRegisterInfo *TRI;
211 TRI = MF->getSubtarget().getRegisterInfo();
338 LaneBitmask UseMask = TRI->getSubRegIndexLaneMask(SubRegIdx);
414 PhysReg = TRI->getSubReg(PhysReg, SubReg)
[all...] |
| RegisterCoalescer.cpp | 86 const TargetRegisterInfo* TRI;
268 static bool isMoveInstr(const TargetRegisterInfo &tri, const MachineInstr *MI,
278 DstSub = tri.composeSubRegIndices(MI->getOperand(0).getSubReg(),
310 if (!isMoveInstr(TRI, MI, Src, Dst, SrcSub, DstSub))
328 Dst = TRI.getSubReg(Dst, DstSub);
335 Dst = TRI.getMatchingSuperReg(Dst, SrcSub, MRI.getRegClass(Src));
351 NewRC = TRI.getCommonSuperRegClass(SrcRC, SrcSub, DstRC, DstSub,
358 NewRC = TRI.getMatchingSuperRegClass(DstRC, SrcRC, DstSub);
362 NewRC = TRI.getMatchingSuperRegClass(SrcRC, DstRC, SrcSub);
365 NewRC = TRI.getCommonSubClass(DstRC, SrcRC)
[all...] |
| MachineInstr.cpp | 77 const TargetRegisterInfo &TRI) {
80 SubIdx = TRI.composeSubRegIndices(SubIdx, getSubReg());
86 void MachineOperand::substPhysReg(unsigned Reg, const TargetRegisterInfo &TRI) {
89 Reg = TRI.getSubReg(Reg, getSubReg());
307 const TargetRegisterInfo *TRI) const {
309 print(OS, DummyMST, TRI);
313 const TargetRegisterInfo *TRI) const {
316 OS << PrintReg(getReg(), TRI, getSubReg());
420 for (unsigned i = 0; i < TRI->getNumRegs(); ++i) {
425 OS << " " << PrintReg(i, TRI);
[all...] |
| DeadMachineInstructionElim.cpp | 34 const TargetRegisterInfo *TRI;
98 TRI = MF.getSubtarget().getRegisterInfo();
146 for (MCSubRegIterator SR(Reg, TRI,/*IncludeSelf=*/true);
162 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
|
| /external/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRLiveRanges.cpp | 114 const SIRegisterInfo *TRI = static_cast<const SIRegisterInfo *>(
134 if (TRI->isSGPRClass(MRI.getRegClass(Def))) {
182 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
188 DEBUG(dbgs() << PrintReg(Reg, TRI, 0)
196 << PrintReg(Reg, TRI, 0)
|
| SIFoldOperands.cpp | 108 const TargetRegisterInfo &TRI) {
121 Old.substVirtReg(New->getReg(), New->getSubReg(), TRI);
203 const SIInstrInfo *TII, const SIRegisterInfo &TRI,
221 TRI.getPhysRegClass(UseReg);
227 TRI.getRegClass(FoldDesc.OpInfo[0].RegClass);
249 TRI.getPhysRegClass(DestReg);
276 CopiesToReplace, TII, TRI, MRI);
307 const SIRegisterInfo &TRI = TII->getRegisterInfo();
357 CopiesToReplace, TII, TRI, MRI);
365 if (updateOperand(Fold, TRI)) {
[all...] |
| R600MachineScheduler.h | 31 const R600RegisterInfo *TRI;
71 DAG(nullptr), TII(nullptr), TRI(nullptr), MRI(nullptr) {
|
| /external/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 34 const TargetRegisterInfo *TRI;
59 const TargetRegisterInfo *TRI) {
78 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
85 for (MCSubRegIterator Subreg(Reg, TRI, /*IncludeSelf=*/true);
193 TrackDefUses(MI, Defs, Uses, TRI);
244 TrackDefUses(NMI, Defs, Uses, TRI);
276 TRI = STI.getRegisterInfo();
|
| ARMFrameLowering.h | 37 const TargetRegisterInfo *TRI) const override;
42 const TargetRegisterInfo *TRI) const override;
|
| ARMHazardRecognizer.cpp | 20 const TargetRegisterInfo &TRI) {
30 return MI->readsRegister(DefMI->getOperand(0).getReg(), &TRI);
|
| /external/eigen/test/ |
| product_mmtr.cpp | 12 #define CHECK_MMTR(DEST, TRI, OP) { \
14 DEST.template triangularView<TRI>() OP; \
16 ref2.template triangularView<TRI>() = ref1; \
|
| /external/llvm/include/llvm/Target/ |
| TargetFrameLowering.h | 122 const TargetRegisterInfo *TRI,
188 const TargetRegisterInfo *TRI) const {
199 const TargetRegisterInfo *TRI) const {
|
| /external/llvm/lib/Target/AArch64/ |
| AArch64DeadRegisterDefinitionsPass.cpp | 38 const TargetRegisterInfo *TRI;
68 if (TRI->regsOverlap(Reg, MO.getReg()))
135 TRI = MF.getSubtarget().getRegisterInfo();
|
| AArch64StorePairSuppress.cpp | 31 const TargetRegisterInfo *TRI;
120 TRI = ST.getRegisterInfo();
145 if (TII->getMemOpBaseRegImmOfs(&MI, BaseReg, Offset, TRI)) {
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.h | 35 const TargetRegisterInfo *TRI) const override {
40 const TargetRegisterInfo *TRI) const override {
73 const TargetRegisterInfo *TRI, std::vector<CalleeSavedInfo> &CSI)
|
| /external/llvm/include/llvm/CodeGen/ |
| LiveRegMatrix.h | 39 const TargetRegisterInfo *TRI;
|
| RegisterPressure.h | 38 void dump(const TargetRegisterInfo *TRI) const;
141 LLVM_DUMP_METHOD void dump(const TargetRegisterInfo &TRI) const;
267 const TargetRegisterInfo *TRI;
303 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
307 MF(nullptr), TRI(nullptr), RCI(nullptr), LIS(nullptr), MBB(nullptr), P(rp),
452 const TargetRegisterInfo *TRI);
|
| /external/llvm/lib/CodeGen/AsmPrinter/ |
| DbgValueHistoryCalculator.h | 56 const TargetRegisterInfo *TRI,
|
| /external/llvm/lib/Target/Mips/ |
| MipsSEFrameLowering.h | 36 const TargetRegisterInfo *TRI) const override;
|
| MipsSEInstrInfo.h | 55 const TargetRegisterInfo *TRI,
62 const TargetRegisterInfo *TRI,
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.h | 34 const X86RegisterInfo *TRI;
82 const TargetRegisterInfo *TRI,
88 const TargetRegisterInfo *TRI) const override;
93 const TargetRegisterInfo *TRI) const override;
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZElimCompare.cpp | 60 : MachineFunctionPass(ID), TII(nullptr), TRI(nullptr) {}
82 const TargetRegisterInfo *TRI;
135 if (TRI->regsOverlap(MOReg, Reg)) {
299 int CCDef = MI->findRegisterDefOperandIdx(SystemZ::CC, false, true, TRI);
306 MBBI->clearRegisterKills(SystemZ::CC, TRI);
398 if (MBBI->modifiesRegister(SrcReg, TRI) ||
399 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
409 int CCUse = MBBI->findRegisterUseOperandIdx(SystemZ::CC, false, TRI);
428 MBBI->clearRegisterKills(SrcReg, TRI);
430 MBBI->clearRegisterKills(SrcReg2, TRI);
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCFrameLowering.h | 81 const TargetRegisterInfo *TRI) const override;
90 const TargetRegisterInfo *TRI) const override;
|
