| /external/llvm/lib/Target/AArch64/ |
| AArch64PBQPRegAlloc.cpp | 166 if (TRI->isPhysicalRegister(Rd) || TRI->isPhysicalRegister(Ra)) {
167 DEBUG(dbgs() << "Rd is a physical reg:" << TRI->isPhysicalRegister(Rd)
169 DEBUG(dbgs() << "Ra is a physical reg:" << TRI->isPhysicalRegister(Ra)
197 if (livesOverlap && TRI->regsOverlap(pRd, pRa))
250 DEBUG(dbgs() << "Moving acc chain from " << PrintReg(Ra, TRI) << " to "
251 << PrintReg(Rd, TRI) << '\n';);
256 DEBUG(dbgs() << "Creating new acc chain for " << PrintReg(Rd, TRI)
331 TRI = MF.getSubtarget().getRegisterInfo();
343 DEBUG(dbgs() << "Killing chain " << PrintReg(r, TRI) << " at "
[all...] |
| AArch64A57FPLoadBalancing.cpp | 117 const TargetRegisterInfo *TRI;
319 TRI = F.getRegInfo().getTargetRegisterInfo();
501 BitVector AvailableRegs = RS.getRegsAvailable(TRI->getRegClass(RegClassID));
505 AvailableRegs &= RS.getRegsAvailable(TRI->getRegClass(RegClassID));
514 MCRegAliasIterator AI(J.getReg(), TRI, /*IncludeSelf=*/true);
529 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID));
554 DEBUG(dbgs() << " - Scavenged register: " << TRI->getName(Reg) << "\n");
630 << TRI->getName(DestReg) << " at " << *MI);
650 << TRI->getName(AccumReg) << " in MI " << *MI);
675 << TRI->getName(DestReg) << "\n")
[all...] |
| AArch64LoadStoreOptimizer.cpp | 87 const TargetRegisterInfo *TRI;
765 unsigned DstRegW = TRI->getSubReg(DstRegX, AArch64::sub_32);
807 const TargetRegisterInfo *TRI) {
816 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
820 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
890 if (FirstMI->modifiesRegister(BaseReg, TRI))
904 ModifiedRegs.resize(TRI->getNumRegs());
905 UsedRegs.resize(TRI->getNumRegs());
960 trackRegDefsUses(MI, ModifiedRegs, UsedRegs, TRI);
[all...] |
| /external/llvm/lib/Target/ARM/ |
| A15SDOptimizer.cpp | 61 const TargetRegisterInfo *TRI;
151 unsigned DReg = TRI->getMatchingSuperReg(SReg, ARM::ssub_1,
160 if (!TRI->isVirtualRegister(SReg))
202 if (!TRI->isVirtualRegister(Reg))
225 if (!TRI->isVirtualRegister(DefReg)) {
261 if (TRI->isVirtualRegister(DPRReg) && TRI->isVirtualRegister(SPRReg)) {
311 if (!TRI->isVirtualRegister(OpReg))
355 if (!TRI->isVirtualRegister(MI->getOperand(1).getReg()))
383 if (!TRI->isVirtualRegister(Reg))
[all...] |
| ARMBaseInstrInfo.cpp | 799 const TargetRegisterInfo *TRI = &getRegisterInfo();
803 if (TRI->regsOverlap(SrcReg, TRI->getSubReg(DestReg, BeginIdx))) {
811 unsigned Dst = TRI->getSubReg(DestReg, BeginIdx + i * Spacing);
812 unsigned Src = TRI->getSubReg(SrcReg, BeginIdx + i * Spacing);
828 Mov->addRegisterDefined(DestReg, TRI);
830 Mov->addRegisterKilled(SrcReg, TRI);
836 const TargetRegisterInfo *TRI) const {
841 return MIB.addReg(TRI->getSubReg(Reg, SubIdx), State);
849 const TargetRegisterInfo *TRI) const
[all...] |
| /external/llvm/lib/Target/PowerPC/ |
| PPCVSXFMAMutate.cpp | 68 const TargetRegisterInfo *TRI = &TII->getRegisterInfo();
161 if (J->modifiesRegister(AddendSrcReg, TRI) ||
162 J->killsRegister(AddendSrcReg, TRI)) {
273 UseMO.substVirtReg(KilledProdReg, KilledProdSubReg, *TRI);
299 for (MCRegUnitIterator Units(AddendSrcReg, TRI); Units.isValid();
|
| /external/llvm/lib/Target/SystemZ/ |
| SystemZShortenInst.cpp | 48 const TargetRegisterInfo *TRI;
81 unsigned GR64BitReg = TRI->getMatchingSuperReg(Reg, thisSubRegIdx,
83 unsigned OtherReg = TRI->getSubReg(GR64BitReg, otherSubRegIdx);
269 TRI = ST.getRegisterInfo();
270 LiveRegs.init(TRI);
|
| /external/llvm/lib/Target/Hexagon/ |
| HexagonFrameLowering.cpp | 195 unsigned getMax32BitSubRegister(unsigned Reg, const TargetRegisterInfo &TRI,
201 for (MCSubRegIterator SubRegs(Reg, &TRI); SubRegs.isValid(); ++SubRegs) {
215 const TargetRegisterInfo &TRI) {
221 unsigned Max = getMax32BitSubRegister(CSI[0].getReg(), TRI);
223 unsigned Reg = getMax32BitSubRegister(CSI[I].getReg(), TRI);
[all...] |
| HexagonCopyToCombine.cpp | 61 const TargetRegisterInfo *TRI;
169 static bool areCombinableOperations(const TargetRegisterInfo *TRI,
207 const TargetRegisterInfo *TRI) {
208 return (UseReg && (I->modifiesRegister(UseReg, TRI))) ||
209 I->modifiesRegister(DestReg, TRI) ||
210 I->readsRegister(DestReg, TRI) ||
230 if (I2UseReg && I1->modifiesRegister(I2UseReg, TRI))
260 if (isUnsafeToMoveAcross(&*I, I2UseReg, I2DestReg, TRI)) {
267 I->readsRegister(KilledOperand, TRI))
273 bool Added = KillingInstr->addRegisterKilled(KilledOperand, TRI, true)
[all...] |
| HexagonSplitConst32AndConst64.cpp | 79 const TargetRegisterInfo *TRI = Fn.getSubtarget().getRegisterInfo();
139 unsigned DestLo = TRI->getSubReg(DestReg, Hexagon::subreg_loreg);
140 unsigned DestHi = TRI->getSubReg(DestReg, Hexagon::subreg_hireg);
|
| HexagonNewValueJump.cpp | 112 const TargetRegisterInfo *TRI,
161 if (localBegin->modifiesRegister(Reg, TRI) ||
162 localBegin->readsRegister(Reg, TRI))
214 const TargetRegisterInfo *TRI,
266 if (localII->modifiesRegister(pReg, TRI) ||
267 localII->readsRegister(pReg, TRI))
277 if (localII->modifiesRegister(cmpReg1, TRI) ||
278 (secondReg && localII->modifiesRegister(cmpOp2, TRI)))
|
| HexagonGenPredicate.cpp | 51 PrintRegister(Register R, const TargetRegisterInfo &I) : Reg(R), TRI(I) {}
55 const TargetRegisterInfo &TRI;
60 return OS << PrintReg(PR.Reg.R, &PR.TRI, PR.Reg.S);
66 HexagonGenPredicate() : MachineFunctionPass(ID), TII(0), TRI(0), MRI(0) {
85 const HexagonRegisterInfo *TRI;
208 << PrintReg(Reg.R, TRI, Reg.S) << "\n");
212 DEBUG(dbgs() << "Dead reg: " << PrintReg(Reg.R, TRI, Reg.S) << '\n');
235 DEBUG(dbgs() << LLVM_FUNCTION_NAME << ": " << PrintRegister(Reg, *TRI));
243 DEBUG(dbgs() << " -> " << PrintRegister(PR, *TRI) << '\n');
259 DEBUG(dbgs() << " -> !" << PrintRegister(Register(NewPR), *TRI) << '\n')
[all...] |
| /external/llvm/lib/CodeGen/ |
| RegAllocPBQP.cpp | 366 const TargetRegisterInfo &TRI =
385 if (TRI.regsOverlap(PRegN, PRegM)) {
545 static bool isACalleeSavedRegister(unsigned reg, const TargetRegisterInfo &TRI,
547 const MCPhysReg *CSR = TRI.getCalleeSavedRegs(&MF);
549 if (TRI.regsOverlap(reg, CSR[i]))
560 const TargetRegisterInfo &TRI =
590 for (MCRegUnitIterator Units(PReg, &TRI); Units.isValid(); ++Units) {
617 if (isACalleeSavedRegister(VRegAllowed[i], TRI, MF))
637 const TargetRegisterInfo &TRI = *MF.getSubtarget().getRegisterInfo();
638 (void)TRI;
[all...] |
| ProcessImplicitDefs.cpp | 30 const TargetRegisterInfo *TRI;
108 !TRI->regsOverlap(Reg, UserReg))
143 TRI = MF.getSubtarget().getRegisterInfo();
|
| RegAllocBase.cpp | 60 TRI = &vrm.getTargetRegInfo();
106 << TRI->getRegClassName(MRI->getRegClass(VirtReg->reg))
|
| ExecutionDepsFix.cpp | 139 const TargetRegisterInfo *TRI;
208 /// Translate TRI register number to a list of indices into our smaller tables
506 unsigned Pref = TII->getUndefRegClearance(MI, OpNum, TRI);
524 DEBUG(dbgs() << TRI->getName(RC->getRegister(rx)) << ":\t" << CurInstr
529 unsigned Pref = TII->getPartialRegUpdateClearance(MI, i, TRI);
531 TII->breakPartialRegDependency(MI, i, TRI);
555 LiveRegSet.init(TRI);
567 TII->breakPartialRegDependency(UndefMI, OpIdx, TRI);
724 TRI = MF->getSubtarget().getRegisterInfo();
729 << TRI->getRegClassName(RC) << " **********\n")
[all...] |
| LiveIntervalAnalysis.cpp | 124 TRI = MF->getSubtarget().getRegisterInfo();
146 for (unsigned i = 0, e = TRI->getNumRegUnits(); i != e; ++i)
160 OS << PrintRegUnit(i, TRI) << ' ' << *LR << '\n';
230 if (const uint32_t *Mask = MBB.getBeginClobberMask(TRI)) {
245 if (const uint32_t *Mask = MBB.getEndClobberMask(TRI)) {
278 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
279 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
288 for (MCRegUnitRootIterator Roots(Unit, TRI); Roots.isValid(); ++Roots) {
289 for (MCSuperRegIterator Supers(*Roots, TRI, /*IncludeSelf=*/true);
308 RegUnitRanges.resize(TRI->getNumRegUnits())
[all...] |
| MachineVerifier.cpp | 68 const TargetRegisterInfo *TRI;
94 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs)
188 return Reg < TRI->getNumRegs() && MRI->isAllocatable(Reg);
298 TRI = MF.getSubtarget().getRegisterInfo();
434 MO->print(errs(), TRI);
444 errs() << "- register: " << PrintReg(Reg, TRI) << '\n';
475 for (MCSubRegIterator SubRegs(Reg, TRI); SubRegs.isValid(); ++SubRegs) {
699 for (MCSubRegIterator SubRegs(LI.PhysReg, TRI, /*IncludeSelf=*/true);
709 for (MCSubRegIterator SubRegs(I, TRI, /*IncludeSelf=*/true);
[all...] |
| /external/llvm/include/llvm/CodeGen/ |
| LiveVariables.h | 132 const TargetRegisterInfo *TRI;
204 if (MI->addRegisterKilled(IncomingReg, TRI, AddIfNotFound))
240 if (MI->addRegisterDead(IncomingReg, TRI, AddIfNotFound))
|
| VirtRegMap.h | 43 const TargetRegisterInfo *TRI;
86 const TargetRegisterInfo &getTargetRegInfo() const { return *TRI; }
|
| RegisterClassInfo.h | 52 const TargetRegisterInfo *TRI;
117 /// This is the smallest value returned by TRI->getCostPerUse(Reg) for all
126 /// same cost according to TRI->getCostPerUse().
|
| /external/llvm/lib/Target/AMDGPU/ |
| SILowerI1Copies.cpp | 77 const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
111 TRI->getCommonSubClass(SrcRC, &AMDGPU::SGPR_64RegClass)) {
137 } else if (TRI->getCommonSubClass(DstRC, &AMDGPU::SGPR_64RegClass) &&
|
| /external/llvm/lib/Target/X86/ |
| X86FrameLowering.cpp | 42 STI(STI), TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {
44 SlotSize = TRI->getSlotSize();
49 StackPtr = TRI->getStackRegister();
64 (hasFP(MF) && !TRI->needsStackRealignment(MF)) ||
65 TRI->hasBasePointer(MF);
89 TRI->needsStackRealignment(MF) ||
149 const X86RegisterInfo *TRI,
156 const TargetRegisterClass &AvailableRegs = *TRI->getGPRsForTailCall(*MF);
181 for (MCRegAliasIterator AI(Reg, TRI, true); AI.isValid(); ++AI)
266 Reg = findDeadCallerSavedReg(MBB, MBBI, TRI, Is64Bit)
[all...] |
| /external/llvm/lib/Target/Mips/ |
| Mips16InstrInfo.h | 55 const TargetRegisterInfo *TRI,
62 const TargetRegisterInfo *TRI,
|
| /external/llvm/lib/CodeGen/SelectionDAG/ |
| InstrEmitter.cpp | 135 RC = TRI->getAllocatableClass(
136 TII->getRegClass(II, i+II.getNumDefs(), TRI, *MF));
142 TRI->getCommonSubClass(UseRC, RC, VT.SimpleTy);
157 SrcRC = TRI->getMinimalPhysRegClass(SrcReg, VT);
221 TRI->getAllocatableClass(TII->getRegClass(II, i, TRI, *MF));
230 VTRC = TRI->getCommonSubClass(RC, VTRC);
335 DstRC = TRI->getAllocatableClass(TII->getRegClass(*II,IIOpNum,TRI,*MF));
445 const TargetRegisterClass *RC = TRI->getSubClassWithSubReg(VRC, SubIdx)
[all...] |
