| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/mips/ |
| micromips@hilo-diff-eb.d | 9 [0-9a-f]+ <[^>]*> 3080 0000 li a0,0
10 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
11 [0-9a-f]+ <[^>]*> 3084 7ffc addiu a0,a0,32764
12 [0-9a-f]+ <[^>]*> 30a0 0000 li a1,0
15 [0-9a-f]+ <[^>]*> 3080 0000 li a0,0
16 [0-9a-f]+ <[^>]*> 0084 8000 sll a0,a0,0x10
17 [0-9a-f]+ <[^>]*> 3084 7ffc addiu a0,a0,3276
[all...] |
| vxworks1-el.d | 13 .*: 8f840000 lw a0,0\(gp\)
18 .*: 8f840000 lw a0,0\(gp\)
23 .*: 8f840000 lw a0,0\(gp\)
25 .*: 8c840000 lw a0,0\(a0\)
29 .*: 8f840000 lw a0,0\(gp\)
31 .*: 8c840000 lw a0,0\(a0\)
37 .*: ac240000 sw a0,0\(at\)
43 .*: ac240000 sw a0,0\(at\
[all...] |
| vxworks1.d | 12 .*: 8f840000 lw a0,0\(gp\)
17 .*: 8f840000 lw a0,0\(gp\)
22 .*: 8f840000 lw a0,0\(gp\)
24 .*: 8c840000 lw a0,0\(a0\)
28 .*: 8f840000 lw a0,0\(gp\)
30 .*: 8c840000 lw a0,0\(a0\)
36 .*: ac240000 sw a0,0\(at\)
42 .*: ac240000 sw a0,0\(at\
[all...] |
| elf-rel19.d | 12 .*: 8f840000 lw a0,0\(gp\)
15 .*: 24840000 addiu a0,a0,0
20 .*: 8f840000 lw a0,0\(gp\)
23 .*: 24840002 addiu a0,a0,2
28 .*: 8f840000 lw a0,0\(gp\)
33 .*: 00812021 addu a0,a0,at
|
| elf-rel16.d | 10 .*: 8f840000 lw a0,0\(gp\)
12 .*: dc840000 ld a0,0\(a0\)
|
| elf-rel17.d | 9 .*: 3c040000 lui a0,0x0
11 .*: 24840000 addiu a0,a0,0
|
| pcrel-1.d | 9 0: 3c040001 lui a0,0x1
10 4: 2484800c addiu a0,a0,-32756
|
| mips16-hilo-n32.d | 11 0: 6c00 li a0,0
12 2: f400 3480 sll a0,16
13 6: 4c00 addiu a0,0
14 8: f000 6c00 li a0,0
16 c: f400 3480 sll a0,16
17 10: f000 4c00 addiu a0,0
19 14: f000 6c00 li a0,0
21 18: f400 3480 sll a0,16
22 1c: f000 4c00 addiu a0,0
24 20: f000 6c00 li a0,
[all...] |
| mips16-hilo.d | 11 0: 6c00 li a0,0
12 2: f400 3480 sll a0,16
13 6: 4c00 addiu a0,0
14 8: f000 6c00 li a0,0
16 c: f400 3480 sll a0,16
17 10: f000 4c00 addiu a0,0
19 14: f000 6c00 li a0,0
21 18: f400 3480 sll a0,16
22 1c: f000 4c04 addiu a0,4
24 20: f000 6c00 li a0,
[all...] |
| ulh-xgot.d | 17 0+0010 <[^>]*> lb a0,0\(at\)
19 0+0018 <[^>]*> sll a0,a0,0x8
20 0+001c <[^>]*> or a0,a0,at
27 0+0030 <[^>]*> lbu a0,0\(at\)
29 0+0038 <[^>]*> sll a0,a0,0x8
30 0+003c <[^>]*> or a0,a0,a
[all...] |
| micromips@and.d | 11 [0-9a-f]+ <[^>]*> d084 0000 andi a0,a0,0x0
12 [0-9a-f]+ <[^>]*> d084 0001 andi a0,a0,0x1
13 [0-9a-f]+ <[^>]*> d084 8000 andi a0,a0,0x8000
15 [0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,at
17 [0-9a-f]+ <[^>]*> 0024 2250 and a0,a0,a
[all...] |
| mips-abi32.s | 15 li $4, 0x12345678 # 0000 lui a0,0x1234
16 # 0004 ori a0,a0,0x5678
17 la $4, shared # 0008 addiu a0,gp,shared
18 la $4, unshared # 000c lui a0,hi(unshared)
19 # 0010 addiu a0,a0,lo(unshared)
20 la $4, end # 0014 lui a0,hi(end)
21 # 0018 addiu a0,a0,lo(end
[all...] |
| mips-gp32-fp32.s | 15 li $4, 0x12345678 # 0000 lui a0,0x1234
16 # 0004 ori a0,a0,0x5678
17 la $4, shared # 0008 addiu a0,gp,shared
18 la $4, unshared # 000c lui a0,hi(unshared)
19 # 0010 addiu a0,a0,lo(unshared)
20 la $4, end # 0014 lui a0,hi(end)
21 # 0018 addiu a0,a0,lo(end
[all...] |
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/m68k/ |
| p3041pcrel.s | 1 lea mytext(%pc),%a0
2 lea mytext+2(%pc),%a0
3 lea mytext-4(%pc),%a0
4 lea mydata(%pc),%a0
5 lea mydata+3(%pc),%a0
6 lea mydata-1(%pc),%a0
7 lea mybss(%pc),%a0
8 lea mybss+1(%pc),%a0
9 lea mybss-2(%pc),%a0
|
| p3041.d | 14 0: 41f9 0000 0000 lea 0 <.*>,%a0
16 6: 41f9 0000 0002 lea 2 <.*>,%a0
18 c: 41f9 ffff fffc lea fffffffc <.*>,%a0
20 12: 41f9 0000 0000 lea 0 <.*>,%a0
22 18: 41f9 0000 0003 lea 3 <.*>,%a0
24 1e: 41f9 ffff ffff lea ffffffff <.*>,%a0
26 24: 41f9 0000 0000 lea 0 <.*>,%a0
28 2a: 41f9 0000 0001 lea 1 <.*>,%a0
30 30: 41f9 ffff fffe lea fffffffe <.*>,%a0
|
| cpu32.s | 15 tblub (%a0),%d1
16 tbluw (%a0),%d1
17 tblul (%a0),%d1
18 tblunb (%a0),%d1
19 tblunw (%a0),%d1
20 tblunl (%a0),%d1
21 tblsb (%a0),%d1
22 tblsw (%a0),%d1
23 tblsl (%a0),%d1
24 tblsnb (%a0),%d
[all...] |
| operands.s | 9 tstl %a0
12 tstl %a0@
13 tstl (%a0)
16 tstl %a0@+
17 tstl (%a0)+
20 tstl %a0@-
21 tstl -(%a0)
24 tstl %a0@(8)
25 tstl (8,%a0)
26 tstl 8(%a0)
[all...] |
| /art/runtime/interpreter/mterp/mips/ |
| binop.S | 1 %default {"preinstr":"", "result":"a0", "chkzero":"0"}
4 * specifies an instruction that performs "result = a0 op a1".
6 * comes back in a register other than a0, you can override "result".)
17 FETCH(a0, 1) # a0 <- CCBB
19 srl a3, a0, 8 # a3 <- CC
20 and a2, a0, 255 # a2 <- BB
22 GET_VREG(a0, a2) # a0 <- vBB
30 $instr # $result <- op, a0-a3 change
[all...] |
| op_const.S | 3 FETCH(a0, 1) # a0 <- bbbb (low)
7 or a0, a1, a0 # a0 <- BBBBbbbb
9 SET_VREG_GOTO(a0, a3, t0) # vAA <- a0
|
| op_aget_wide.S | 7 FETCH(a0, 1) # a0 <- CCBB
9 and a2, a0, 255 # a2 <- BB
10 srl a3, a0, 8 # a3 <- CC
11 GET_VREG(a0, a2) # a0 <- vBB (array object)
14 beqz a0, common_errNullObject # yes, bail
15 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
16 EAS3(a0, a0, a1) # a0 <- arrayObj + index*widt
[all...] |
| op_aput_wide.S | 7 FETCH(a0, 1) # a0 <- CCBB
9 and a2, a0, 255 # a2 <- BB
10 srl a3, a0, 8 # a3 <- CC
11 GET_VREG(a0, a2) # a0 <- vBB (array object)
14 beqz a0, common_errNullObject # yes, bail
15 LOAD_base_offMirrorArray_length(a3, a0) # a3 <- arrayObj->length
16 EAS3(a0, a0, a1) # a0 <- arrayObj + index*widt
[all...] |
| /art/runtime/interpreter/mterp/mips64/ |
| op_iput_wide_quick.S | 5 ext a0, rINST, 8, 4 # a0 <- A
7 GET_VREG_WIDE a0, a0 # a0 <- fp[A]
10 sw a0, 0(a1)
11 dsrl32 a0, a0, 0
12 sw a0, 4(a1)
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/i386/ |
| relax-1.d | 10 e: e9 8d 00 00 00 jmp (0x)?a0( .*)?
12 21: eb 7d jmp (0x)?a0( .*)?
14 a0: 90 nop
|
| /toolchain/binutils/binutils-2.25/gas/testsuite/gas/tic6x/ |
| predicate-bad-3.s | 17 [!a0] ddotph2 .M2 b1:b0,b2,b5:b4
18 [!a0] ddotph2r .M2 b1:b0,b2,b5
19 [!a0] ddotpl2 .M2 b1:b0,b2,b5:b4
20 [!a0] ddotpl2r .M2 b1:b0,b2,b5
22 [a0] dpack2 .L1 a0,a1,a3:a2
23 [b0] dpackx2 .L1 a0,a1,a3:a2
27 [a0] rint
28 [b0] rpack2 .S1 a0,a1,a2
29 [!b1] saddsub .L1 a0,a0,a1:a
[all...] |
| insns-bad-1.s | 21 abs .L1 A0,A00
35 abs .L1X B1:B0,A1:A0
36 abs .L1 A1:A0,A11
41 absdp .L1 a3:a2,a1:a0
44 absdp .S2X a1:a0,b1:b0
45 abssp .L1 a0,a0
46 abssp .S1 a1:a0
47 abssp .S1X a0,a1
49 add .M1 a0,a0,a
[all...] |
